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pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use pm5343 stxc sonet/sdh transport overhead transceiver telecom standard product data sheet issue 6: september 1998
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use revision history issue no. issue date details of change issue 6 september, 1998 1. name of pecl input parameter changed from vpia to vpswg. spec. revised to 550 mv to reflect characterization results 2. clarified usage of mbeb and csb signals in test feature description section. 3. clarified conditions required for test mode 0 access to rin and scpi/scpo signals 4. improved description of register 1ah. 5. pin descriptions for griclk/riclk and gticlk/ticlk in bit-serial mode was improved. 6. bit error rate tables added to meet itu specs. 7. iddop2 spec improved 8. tifp pin description corrected. 9. changed lead temperature max rating to 230 deg 10. changed all references from pqfp to more technically correct mqfp. 11. changed pecl pin types from input and output to pecl input and pecl output. issue 5 september, 1997 re-formatted to fit new template.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use i contents 1 features ............................................................................................ 1 2 applications ..................................................................................... 3 3 references ...................................................................................... 4 4 application example ..................................................................... 5 5 block diagram................................................................................. 6 6 description ...................................................................................... 7 7 pin diagram ....................................................................................... 9 8 pin description ............................................................................. 10 9 functional description ............................................................ 36 9.1 serial to parallel converter...................................... 36 9.2 receive section overhead processor..................... 36 9.3 receive line overhead processor ............................ 37 9.4 receive transport overhead access....................... 39 9.5 ring control port............................................................ 39 9.6 transmit transport overhead access .................... 40 9.7 transmit line overhead processor .......................... 40 9.8 transmit section overhead processor .................. 41 9.9 parallel to serial converter...................................... 42 9.10 receive section trace buffer ..................................... 42 9.11 transmit section trace buffer................................... 43 9.12 microprocessor interface .......................................... 43 10 register description................................................................. 44
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use ii 11 test features description .................................................... 129 12 functional timing ...................................................................... 135 13 operation ..................................................................................... 152 13.1 bit error rate monitor................................................. 152 14 absolute maximum ratings..................................................... 155 15 d.c. characteristics ................................................................. 156 16 microprocessor interface timing characteristics ......................................................................... 161 17 stxc timing characteristics ................................................. 169 17.1 input timing........................................................................ 169 17.2 output timing.................................................................... 176 18 ordering and thermal information ................................... 181 19 mechanical information.......................................................... 182
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use iii list of registers address 00h: master configuration ............................................... 47 address 01h: master control/enable ............................................ 50 address 02h: master interrupt status .......................................... 53 address 03h: master reset and identity ....................................... 55 address 04h: tlop control ................................................................. 56 address 05h: tlop diagnostic ............................................................ 59 address 06h: transmit k1 ..................................................................... 60 address 07h: transmit k2 ..................................................................... 61 address 08h: rlop control/status .................................................. 62 address 09h: rlop interrupt enable and status........................ 64 address 0ah: b2 error count #1 ....................................................... 66 address 0bh: b2 error count #2 ....................................................... 66 address 0ch: b2 error count #3 ....................................................... 66 address 0dh: rei error count #1...................................................... 68 address 0eh: rei error count #2...................................................... 68 address 0fh: rei error count #3 ...................................................... 68 address 10h: rsop control ................................................................ 70 address 11h: rsop interrupt status ............................................... 72 address 12h: b1 error count #1........................................................ 74 address 13h: b1 error count #2........................................................ 74 address 14h: output port ................................................................... 75 address 15h: input port interrupt enable................................... 76
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use iv address 16h: mode select ................................................................... 77 address 17h: ring control ................................................................. 79 register 18h: tsop control................................................................ 82 register 19h: tsop diagnostic ........................................................... 85 register 1ah: transmit z1 .................................................................... 86 register 1bh: receive z1 (enh=0) ....................................................... 87 register 1bh: transmit z0 (enh=1) ..................................................... 88 address 1dh: receive k1 (enh=0) ........................................................ 89 address 1dh: ais control (enh=1)..................................................... 90 address 1eh: receive k2 (enh=0) ........................................................ 92 address 1eh: rdi control (enh=1)..................................................... 93 address 1fh: configuration input port status/value .............. 95 register 20h: section trace control (enh=0).............................. 97 register 20h: rase interrupt enable (enh=1) .............................. 99 register 21h: section trace status (enh=0):............................... 101 register 21h: rase interrupt status (enh=1).............................. 103 register 22h: section trace indirect address register (enh=0): ........................................................................ 105 register 22h: rase configuration/control register (enh=1):............................................................................................ 106 register 23h: section trace indirect data register (enh=0)............................................................................................. 108 register 23h: rase sf accumulation period (lsb, enh=1) ....... 109 register 24h: rase sf accumulation period (enh=1)................ 109 register 25h: rase sf accumulation period (msb, enh=1) ...... 109
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use v register 26h: rase sf saturation threshold (lsb, enh=1).............................................................................................. 111 register 27h: rase sf saturation threshold (msb, enh=1).............................................................................................. 111 register 28h: section trace ais insertion (enh=0)................... 112 register 28h: rase sf declaring threshold (lsb, enh=1) ...... 113 register 29h: rase sf declaring threshold (msb, enh=1).............................................................................................. 113 register 2ah: rase sf clearing threshold (lsb, enh=1) ........ 114 register 2bh: rase sf clearing threshold (msb, enh=1) ....... 114 register 2ch: rase sd accumulation period (lsb, enh=1) ...... 115 register 2dh: rase sd accumulation period (enh=1)............... 115 register 2eh: rase sd accumulation period (msb, enh=1).............................................................................................. 115 register 2fh: rase sd saturation threshold (lsb, enh=1).............................................................................................. 117 register 30h: rase sd saturation threshold (msb, enh=1).............................................................................................. 117 register 31h: rase sd declaring threshold (lsb, enh=1).............................................................................................. 118 register 32h: rase sd declaring threshold (msb, enh=1).............................................................................................. 118 register 33h: rase sd clearing threshold (lsb, enh=1) ........ 119 register 34h: rase sd clearing threshold (msb, enh=1) ....... 119 address 35h: receive k1 (enh=1)....................................................... 120 address 36h: receive k2 (enh=1)....................................................... 121 register 37h: receive z1 (enh=1)...................................................... 122
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use vi register 38h: section trace control (enh=1):........................... 123 register 39h: section trace status (enh=1):............................... 125 register 3ah: section trace indirect address register (enh=1) ......................................................................... 127 register 3bh: section trace indirect data register (enh=1)............................................................................................. 128 address 43h: master test.................................................................. 131
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use vii list of figures figure 1 - sts-3/stm-1 line interface................................................. 5 figure 2 - sts-3 bit serial transmit frame pattern and data alignment ....................................................................................... 135 figure 3 - sts-3 byte serial transmit frame pulse and data alignment ....................................................................................... 135 figure 4 - sts-1 bit serial transmit frame pulse and data alignment ....................................................................................... 136 figure 5 - sts-1 byte serial transmit frame pulse and data alignment ....................................................................................... 136 figure 6 - sts-3 bit serial receive frame pattern and data alignment ....................................................................................... 137 figure 7 - sts-3 byte serial receive frame pulse and data alignment ....................................................................................... 137 figure 8 - sts-1 bit serial receive frame pulse and data alignment ....................................................................................... 138 figure 9 - sts-1 byte serial receive frame pulse and data alignment ....................................................................................... 138 figure 10- transport overhead overwrite enable and disable 139 figure 11- in frame declaration (bit serial interface, rser=1) 139 figure 12- in frame declaration (byte serial interface, rser=0) 140 figure 13- out of frame declaration ........................................... 141 figure 14- loss of signal declaration/removal....................... 141 figure 15- loss of frame declaration/removal ....................... 142 figure 16- line ais and line rdi declaration/removal ............. 142
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use viii figure 17- transmit overhead clock and data alignment ................................................................................................ 143 figure 18- receive overhead clock and data alignment....... 144 figure 19- transmit data link clock and data alignment....... 145 figure 20- receive data link clock and data alignment ......... 146 figure 21- b1 and b2 error event occurrence......................... 147 figure 22- transport overhead extraction.............................. 148 figure 23- transport overhead insertion ................................. 149 figure 24- transmit ring control port ....................................... 150 figure 25- receive ring control port ......................................... 151 figure 26- pecl output low voltage.............................................. 159 figure 27- microprocessor interface read access timing (intel mode)................................................................................ 162 figure 28- microprocessor interface read access timing (motorola mode)...................................................................... 163 figure 29- microprocessor interface write access timing (intel mode)................................................................................ 166 figure 30- microprocessor interface write access timing (motorola mode)...................................................................... 167 figure 31- receive input timing........................................................ 170 figure 32- transmit input................................................................... 172 figure 33- sts-3 bit serial input ...................................................... 173 figure 34- sts-1 input .......................................................................... 174 figure 35- transmit ring control port input ........................... 175 figure 36- receive output timing.................................................... 177 figure 37- transmit output timing ................................................. 178
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use ix figure 38- sts-3 bit serial output timing ..................................... 179 figure 39- sts-1 output timing ......................................................... 179 figure 40- ring control port output .......................................... 180 figure 41- 160 pin copper leadframe metric quad flat pack (r suffix): ....................................................................................... 182
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use x list of tables table 1 - normal mode register memory map .......................... 44 table 2 - test mode register memory map............................... 129 table 3 - test mode 0 input observation ................................... 132 table 4 - test mode 0 output control....................................... 133 table 5 - rase-berm configuration for sdh stm-0................ 153 table 6 - rase-berm configuration for sdh stm-1................ 153 table 7 - rase-berm configuration for sonet sts-1............ 154 table 8 - rase-berm configuration for sonet sts-3............ 154 table 9 - stxc absolute maximum ratings ................................ 155 table 10 - stxc d.c. characteristics ............................................ 156 table 11 - microprocessor interface read access (figure 27, figure 28)............................................................................ 161 table 12 - microprocessor interface write access (figure 29, figure 30)............................................................................ 165 table 13 - receive input (figure 31) ............................................... 169 table 14 - transmit input (figure 32)............................................. 170 table 15 - sts-3 bit serial input (figure 33) ................................ 173 table 16 - sts-1 input (figure 34)..................................................... 174 table 17 - transmit ring control port input (figure 35) 175 table 18 - receive output timing (figure 36).............................. 176 table 19 - transmit output timing (figure 37) ........................... 178 table 20 - sts-3 bit serial output (figure 38) ............................ 179
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use xi table 21 - sts-1 output (figure 39)................................................. 179 table 22 - receive ring control port output (figure 40) 180 table 23 - stxc ordering information ......................................... 181 table 24 - stxc thermal information ........................................... 181
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 1 1 features monolithic sonet/sdh transport overhead terminating transceiver for use in sts-1, sts-3 or stm-1 interface applications, operating at serial interface speeds of up to 155.52 mbit/s. provides termination for sonet section and line, and sdh regenerator section and multiplexer section transport overhead. companion to the pm5344 sptx sonet/sdh path terminating transceiver. operates in sts-1 and sts-3 bit-serial (pecl/ttl i/o) and byte-serial (ttl i/o) modes. provides independent control of the transmit and receive operating modes for asymmetrical bandwidth applications. frames to the sts-1 or sts-3 (stm-1) receive stream and inserts the framing bytes (a1, a2) and the sts identification bytes (j0) into the transmit stream; descrambles the receive stream and scrambles the transmit stream. calculates and compares the bit interleaved parity error detection codes (b1, b2) for the receive stream and calculates and inserts b1 and b2 in the transmit stream. accumulates near end errors (b1, b2) and far end errors (m1) and inserts line remote error indications (rei) into the z2 growth byte based on received b2 errors. detects signal degrade (sd) and signal fail (sf) threshold crossing alarms based on received b2 errors. optionally inserts the line bip-8 error detection code into each of the constituent sts-1s (b2 bytes) of the transmit sts-1/3 stream. extracts and serializes the order wire channels (e1, e2), the data communication channels (d1-d3, d4-d12) and the section user channel (f1) from the receive stream, and inserts the corresponding signals into the transmit stream. extracts and serializes the automatic protection switch (aps) channel (k1, k2) bytes, filtering and extracting them into internal registers. inserts the aps channel into the transmit stream.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 2 detects loss of signal (los), out of frame (oof), loss of frame (lof), line remote defect indication (rdi), line alarm indication signal (ais), and protection switching byte failure alarms. inserts and extracts a 64 byte or 16 byte section trace (j0) message using an internal register bank. detects an unstable section trace message or mismatch with an expected message, and inserts line ais upon either of these conditions. inserts rdi and ais in the transmit stream. provides loss of signal insertion, framing pattern error insertion, and coding violation insertion (b1 and b2) for diagnostic purposes. b1 and b2 errors can also be generated "on-the-fly" using an error insertion mask. provides a transmit and receive ring control port, allowing alarm and maintenance signal control and status to be passed between mate stxcs for ring-based add drop multiplexer applications. low power +5 volt 0.8 micron cmos. device has pecl and ttl compatible inputs and outputs. 160 pin copper leadframe mqfp package. supports industrial temperature range (-40c to 85c) operation.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 3 2 applications oc-n regenerators oc-n to oc-m multiplexers sonet/sdh add drop multiplexers sonet/sdh terminal multiplexers broadband isdn user network interfaces sonet/sdh test equipment
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 4 3 references 1. american national standard for telecommunications - digital hierarchy - optical interface rates and formats specification, ansi t1.105-1991. 2. committee t1 contribution, "draft of t1.105 - sonet rates and formats", t1x1.5/94-033r2-1994. 3. itu, recommendation g.707 - "network node interface for the synchronous digital hierarchy", 1996. 4. american national standard for telecommunications - digital hierarchy - optical interface rates and formats specification - supplement, ansi t1.105a-1991. 5. bell communications research - sonet transport systems: common generic criteria, gr-253-core issue 2, december, 1995. 10. etsi de/tm1015, "generic functional requirement for sdh transmission equipment", version 0.4, february 1993.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 5 4 application example the stxc is typically used to implement a portion of an sts-3/stm-1 line interface. the stxc may find application in many different types of sonet/sdh network elements including switches, terminal multiplexers, and add-drop multiplexers. in such applications, the stxc typically interfaces on its line side with a clock and data recovery device (for the receiver) and a physical media device such as a laser (for the transmitter). the system side interfaces directly to the pm5344 sonet/sdh path terminating transceiver (sptx) where pointer processing and path overhead termination are performed for an sts-3/stm-1 stream. the initial configuration and ongoing control and monitoring of the stxc are normally provided via a generic microprocessor interface. figure 1 - sts-3/stm-1 line interface micro bus for config, status and control receive alarm detect signals receive transport overhead access transmit alarm insert signals transmit transport overhead access rsd+/- o/e e/o rxd+/- rxc+/- txd+/- pm5343 stxc 155 mbit/s transport overhead transceiver clock/data recovery txci+/- clock generation micro bus for config, status and control receive alarm detect signals receive path overhead access transmit alarm insert signals transmit path overhead access pm5344 sptx path terminating transceiver gticlk ticlk tifp tin[7:0] tck fpout td[7:0] griclk riclk rofp rout[7:0] piclk ifp rd[7:0] dck dc1j1v1 dd[7:0] dpl ddp telecombus drop interface ack ac1j1v1 ad[7:0] apl adp telecombus add interface
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 6 5 block diagram rout[7:0] aps rx path trace buffer tout[7:0] rin[7:0] riclk rifp tlais/tr cpdat tin[7:0] d[7:0] a[6:0] ale csb rdb_e wrb_ rw b rstb int b microprocessor i/f rx o/h access tx o/h access ttoh rtoh ttohclk rtohclk los/rrcpfp lof rtohfp ttohfp rx section o/h processor rx line o/h processor ttohen trdi/trcpfp lais/rrcpdat rdi/rrcpclk ticlk tofp oof b1e rlais/trcpclk rsdclk rsd rsow rsuc row clk b2e rldclk rld rlow raps rapsclk rofp tifp/tc1j1v1 tdis tx line o/h processor tx section o/h processor tsdclk tsd tso w tsuc tow cl k tldclk tld tlo w taps tapsclk tsout tsiclk serial to parallel rsiclk rsin transmit ring c ontrol port receive ring control port rxd+/- rxc+/- txd+/- txci+/- txco+/- griclk gticlk status and control port scpo[4:0] rser tser mbeb tx section trace buffer rx section trace buffer parallel to serial scpo[5]/rdp scpi[3]/td p scpi[1:0] scpi[2]/t pl
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 7 6 description the pm5343 sonet/sdh 155 mbit/s transport overhead terminating transceiver (stxc) processes the transport overhead (section overhead) of sts-1, and sts-3 (stm-1) streams at 51.84 mbit/s and 155.52 mbit/s. the stxc implements significant functions for a sonet/sdh compliant line interface. the stxc receives sonet/sdh frames via a bit serial or byte serial interface and processes section (regenerator section) and line (multiplexer section) overhead. it performs framing (a1, a2), descrambling, detects alarm conditions, and monitors section and line path bit interleaved parity (b1, b2), accumulating error counts at each level for performance monitoring purposes. b2 errors are also monitored to detect signal fail and signal degrade threshold crossing alarms. line remote error indications (m1) are also accumulated. a 16 or 64 byte section trace (j0) message may be buffered and compared against an expected message. the stxc also provides convenient access to all transport overhead bytes, which are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead. the stxc transmits sonet/sdh frames, via a bit serial or a byte serial interface, and formats section and line overhead appropriately. it performs framing pattern insertion (a1, a2), scrambling, alarm signal insertion, and creates section and line bit interleaved parity (b1, b2) as required to allow performance monitoring at the far end. line remote error indications (m1) are optionally inserted. a 16 or 64 byte section trace (j0) message may be inserted. the stxc also provides convenient access to all transport overhead bytes, which are optionally inserted from lower rate serial interfaces, allowing external sourcing of overhead. the stxc also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors and bit interleaved parity errors, which are useful for system diagnostics and tester applications. ring control ports provide the ability to pass control and status information between mate transceivers. the transmitter and receiver are independently configurable to allow for asymmetric interfaces. the stxc is configured, controlled and monitored via a generic 8-bit microprocessor bus interface.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 8 the stxc is implemented in low power, +5 volt, cmos technology. it has ttl and pseudo ecl (pecl) compatible inputs and outputs and is packaged in a 160 pin mqfp package.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 9 7 pin diagram the stxc is available in a 160 pin mqfp package having a body size of 28 mm by 28 mm and a pin pitch of 0.65 mm. pin 1 pin 160 pm5343 stxc top view pin 40 pin 41 pin 80 pin 81 pin 120 pin 121 tldclk tld towclk tsuc tsow tsdclk tsd rlais/trcpclk tlais/trcpdat trdi/trcpfp tsiclk tser vt1 tavd1 txco- txco+ tavs1 tavd2 tavs2 tavd3 tavs3 txd+ txd- tavs4 vt2 tavd4 txci- txci+ tsout tout[0] tout[1] tout[2] tout[3] vsso vddo tout[4] tout[5] tout[6] tout[7] tofp rifp rin[0] rin[1] rin[2] vddi rin[3] rin[4] rin[5] rin[6] vssi rin[7] rser rsin rsiclk b1e lof oof rx c- rx c+ ravd ravs rx d- rx d+ vddo vsso rsd rsdclk rsow rsuc row clk los/rrcpfp lais/rrcpdat rdi/rrcpclk vddo vssi vddi vsso b2e rld rldclk a[0] a[1] a[2] a[3] a[4] a[5] a[6] rdb_e wrb_rwb csb rstb d[0] d[1] d[2] d[3] d[4] d[5] vddo vsso d[6] d[7] intb scpo[0] scpo[1] scpo[2] scpo[3] scpo[4] scpo[5]/rdp scpi[0] scpi[1] scpi[2]/tpl scpi[3]/tdp rtohclk rtoh vddo vsso rtohfp rapsclk raps rlow rout[7] mbeb ale rout[4] rout[5] rout[6] vsso rout[2] rout[3] rout[0] rout[1] vddo riclk griclk rofp vssi vddo vsso gticlk ticlk vddi tin[3] tin[4] tin[5] tin[0] tin[1] tin[2] ttohclk ttohen tdis ttohfp ttoh vddo tlo w vsso taps tapsclk index tin[6] tin[7] tifp/tc1 j1v1
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 10 8 pin description pin name pin type pin no. function rser input 52 the receive serial input (rser) selects the receive line interface. rser is tied high to select the bit serial interface on pecl pins rxc+, rxc-, rxd+, and rxd-. a ttl interface is also supported in sts-1 mode on pins rsin and rsiclk. rser is tied low to select the byte serial interface (on pins riclk, rin[7:0], and rifp). riclk/ input 135 the receive incoming clock (riclk) provides timing for processing the byte serial receive stream, rin[7:0]. riclk is nominally a 6.48 mhz (sts-1), or 19.44 mhz (sts-3/stm-1) 50% duty cycle clock, depending on the selected operating mode. rin[7:0], and rifp are sampled on the rising edge of riclk. riclk must be externally shorted directly to griclk when processing a bit serial receive stream. rvclk the receive vector clock (rvclk) is used during stxc production test to verify internal functionality. rin[7] rin[6] rin[5] rin[4] rin[3] rin[2] rin[1] rin[0] input input input input input input input input 51 49 48 47 46 44 43 42 the receive incoming stream (rin[7:0]) carries the scrambled sts-1 or sts-3/stm-1 stream in byte serial format. rin[7] is the most significant bit (corresponding to bit 1 of each serial pcm word, the first bit transmitted). rin[0] is the least significant bit (corresponding to bit 8 of each serial pcm word, the last bit transmitted). rin[7:0] is sampled on the rising edge of riclk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 11 pin name pin type pin no. function rifp input 41 the active high receive incoming framing position (rifp) signal indicates when the first byte of the synchronous payload envelope is available on the rin[7:0] inputs. rifp is sampled on the rising edge of riclk. rsin input 53 the receive incoming serial stream (rsin) contains the ttl compatible 51.84 mbit/s receive sts-1 stream. rsin is sampled on the rising edge of rsiclk. the rsin input has an integral pull down resistor. the rxd+/- inputs may also carry the receive sts-1 stream. rsiclk input 54 the receive serial incoming clock (rsiclk) provides timing for processing the bit serial receive stream, rsin when the ttl bit serial sts-1 mode is selected. rsiclk is nominally a 51.84 mhz, 50% duty cycle clock. rsin is sampled on the rising edge of rsiclk. rsiclk is divided by eight to produce griclk when the ttl bit serial sts-1 mode is selected. the rsiclk input has an integral pull down resistor. rxd+ rxd- pecl input 63 62 the receive differential data inputs (rxd+, rxd-) contain the 155.52 mbit/s receive sts- 3/stm-1 or 51.84 mbit/s receive sts-1 stream. rxd+/- is sampled on the rising edge of rxc+/- (the falling edge may be used by reversing rxc+/-). rxc+ rxc- pecl input 59 58 the receive differential clock inputs (rxc+, rxc-) provides timing for processing the bit serial receive stream, rxd+/- when the pecl bit serial mode is selected. rxc+/- is nominally a 155.52 mhz or 51.84 mhz, 50% duty cycle clock. rxd+/- is sampled on the rising edge of rxc+/-. rxc+/- is divided by eight to produce griclk when the pecl bit serial mode is selected.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 12 pin name pin type pin no. function rlais/ input 8 the receive line ais insertion (rlais) signal controls the insertion of line ais in the receive outgoing stream, rout[7:0], when the ring control port is disabled. when rlais is high, line ais is inserted in the outgoing stream. line ais is also optionally inserted automatically upon detection of loss of signal, loss of frame, section trace alarms or line ais in the incoming stream. rlais is sampled on the rising edge of riclk. trcpclk the transmit ring control port clock (trcpclk) signal provides timing for the transmit ring control port when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the master control register). trcpclk is nominally a 3.24 mhz, 50% duty cycle clock and is normally connected to the rrcpclk output of a mate stxc in ring-based add-drop multiplexer applications. trcpfp and trcpdat are sampled on the rising edge of trcpclk. oof output 57 the out of frame (oof) signal is set high while the stxc is unable to find a valid framing pattern (a1, a2) in the incoming stream. oof is set low when a valid framing pattern is detected. oof is updated on the rising edge of riclk. lof output 56 the loss of frame (lof) signal is set high when an out of frame state persists for 3 ms. lof is set low when an in frame state persists for 3 ms. lof is updated on the rising edge of riclk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 13 pin name pin type pin no. function los/ output 71 loss of signal (los) is active when the ring control port is disabled. loss of signal (los) is set high when a violating period (20 2.5 s) of consecutive all zeros patterns is detected in the incoming stream. los is set low when two valid framing words (a1, a2) are detected, and during the intervening time (125 s), no violating period of all zeros patterns is observed. los is updated on the rising edge of riclk. rrcpfp the receive ring control port frame position (rrcpfp) signal identifies bit positions in the receive ring control port data (rrcpdat) when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the master control register). rrcpfp is high during the filtered k1, k2 bit positions, the change of aps value bit position, the protection switch byte failure bit position, and the send ais and send rdi bit positions in the rrcpdat stream. rrcpfp is normally connected to the trcpfp input of a mate stxc in ring-based add-drop multiplexer applications. rrcpfp is updated on the falling edge of rrcpclk. b1e output 55 the b1 error clock (b1e) is a return to zero signal that pulses high for 154 ns with a minimum low time of 154 ns for every section bit interleaved parity error (b1) detected in the incoming stream. up to eight pulses may occur on b1e per frame.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 14 pin name pin type pin no. function rdi/ output 73 the far end receive failure (rdi) signal is active when the ring control port is disabled. rdi is set high when line rdi is detected in the incoming stream. rdi is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. rdi is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. this alarm indication is also available through register access. rdi is updated on the rising edge of riclk. rrcpclk the receive ring control port clock (rrcpclk) signal provides timing for the receive ring control port when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the master control register). rrcpclk is nominally a 3.24 mhz, 50% duty cycle clock and is normally connected to the trcpclk input of a mate stxc in ring-based add-drop multiplexer applications. rrcpfp and rrcpdat are updated on the falling edge of rrcpclk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 15 pin name pin type pin no. function lais/ output 72 the line alarm indication (lais) signal is active when the ring control port is disabled. lais is set high when line ais is detected in the incoming stream. lais is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. lais is removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. this alarm indication is also available through register access. lais is updated on the rising edge of riclk. rrcpdat the receive ring control port data (rrcpdat) signal contains the receive ring control port data stream when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the master control register). the receive ring control port data consists of the filtered k1, k2 byte values, the change of aps value bit position, the protection switch byte failure status bit position, the send ais and send rdi bit positions, and the line rei bit positions. rrcpdat is normally connected to the trcpdat input of a mate stxc in ring-based add-drop multiplexer applications. rrcpdat is updated on the falling edge of rrcpclk. b2e output 78 the b2 error clock (b2e) is a return to zero signal that pulses 154 ns with a minimum low time of 154 ns for every line bit interleaved parity error (b2) detected in the incoming stream. up to 8 (sts-1), or 24 (sts-3/stm-1) pulses may occur on b2e, per frame. rsdclk output 67 the receive section dcc clock (rsdclk) is a 192 khz clock used to update the rsd output. rsdclk is generated by gapping a 216 khz clock.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 16 pin name pin type pin no. function rsd output 66 the receive section dcc (rsd) signal contains the section data communications channel (d1, d2, d3) extracted from the incoming stream. rsd is updated on the falling edge of rsdclk. rowclk output 70 the receive order wire clock (rowclk) is a 64 khz clock used to update the rsow, rsuc, and rlow outputs. rowclk is generated by gapping a 72 khz clock. rsow output 68 the receive section order wire (rsow) signal contains the section order wire channel (e1) extracted from the incoming stream. rsow is updated on the falling edge of rowclk. rsuc output 69 the receive section user channel (rsuc) signal contains the section user channel (f1) extracted from the incoming stream. rsuc is updated on the falling edge of rowclk. rlow output 81 the receive line order wire (rlow) signal contains the line order wire channel (e2) extracted from the incoming stream. rlow is updated on the falling edge of rowclk. rldclk output 80 the receive line dcc clock (rldclk) is a 576 khz clock used to update the rld output. rldclk is generated by gapping a 2.16 mhz clock. rld output 79 the receive line dcc (rld) signal contains the line data communications channel (d4 - d12) extracted from the incoming stream. rld is updated on the falling edge of rldclk. rapsclk output 83 the receive automatic protection switch channel clock (rapsclk) is a 128 khz clock used to update the raps output. rapsclk is generated by gapping a 144 khz clock.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 17 pin name pin type pin no. function raps output 82 the receive automatic protection switch channel (raps) signal carries the automatic protection switch channel (k1, k2) extracted from the incoming stream. raps is updated on the falling edge of rapsclk. rtoh output 87 the receive transport overhead (rtoh) signal contains the receive transport overhead bytes (a1, a2, j0, z0, b1, e1, f1, d1-d3, h1-h3, b2, k1, k2, d4-d12, z1, z2, and e2) extracted from the incoming stream. rtoh is updated on the falling edge of rtohclk. rtohclk output 88 the receive transport overhead clock (rtohclk) is nominally a 5.184 mhz or 1.728 mhz clock that provides timing to process the extracted receive transport overhead, rtoh. rtohclk is a gapped 6.48 mhz clock when accessing the transport overhead of an sts- 3/stm-1 stream. rtohclk is a gapped 2.16 mhz clock when accessing the transport overhead of an sts-1 stream. rtohfp output 84 the receive transport overhead frame position (rtohfp) signal is used to locate the individual receive transport overhead bits in the receive transport overhead, rtoh. rtohfp is set high while bit 1 (the most significant bit) of the first framing byte (a1) is present in the rtoh stream. rtohfp is updated on the falling edge of rtohclk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 18 pin name pin type pin no. function griclk output 134 when either of the bit serial receive interfaces are enabled, griclk is the generated byte serial clock. when the bit serial sts-1 mode is enabled, griclk is a 6.48 mhz clock that is generated by dividing the receive serial incoming clock (rsiclk) by eight. when the bit serial sts-3 mode is enabled, griclk is a 19.44 mhz clock that is generated by dividing the receive serial incoming clock (rsc+/-) by eight. griclk must be externally shorted directly to the receive incoming clock (riclk) when processing a bit serial stream. rout[7] rout[6] rout[5] rout[4] rout[3] rout[2] rout[1] rout[0] output output output output output output output output 123 124 125 126 127 128 131 132 rout[7:0] contains the descrambled outgoing stream in byte serial format. rout[7] is the most significant bit (corresponding to bit 1 of each serial pcm word, the first bit received). rout[0] is the least significant bit (corresponding to bit 8 of each serial pcm word). rout[7:0] is updated on the rising edge of riclk. rofp output 133 the active high receive outgoing frame position (rofp) signal is set high once per frame in the byte position immediately following the z0 bytes in the rout[7:0] stream. rofp is also used to mark the alignment of the rsow, rsuc, rlow and raps bit streams. rofp is updated on the rising edge of riclk. tser input 12 the transmit serial input (tser) selects the transmit line interface. tser is tied high to select the bit serial interface on pecl pins txci+, txci-, txco+, txco-, txd+, and txd-. a ttl interface is also supported in sts-1 mode on pins tsiclk and tsout. tser is tied low to select the byte serial interface on pins ticlk, tofp, and tout[7:0].
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 19 pin name pin type pin no. function ticlk/ input 140 the transmit incoming clock (ticlk) provides timing for processing the transmit stream, tin[7:0]. ticlk is nominally a 6.48 mhz (sts- 1), or 19.44 mhz (sts-3/stm-1) 50% duty cycle clock, depending on the selected operating mode. tin[7:0], and tifp are sampled on the rising edge of ticlk. ticlk must be externally shorted directly to gticlk when processing bit serial transmit streams. tvclk the transmit vector clock (tvclk) is used during stxc production test to verify internal functionality. gticlk output 141 when either of the bit serial transmit interfaces are enabled, gticlk is the generated byte serial clock. gticlk is a 6.48 mhz or 19.44 mhz clock that is generated by dividing the transmit serial incoming clock (tsiclk or txci+/-) by eight. gticlk must be externally shorted directly to the transmit incoming clock (ticlk) when processing a bit serial stream. in line loopback mode operation (lle bit set high), gticlk is generated by dividing the rxc+/- inputs by eight. tsiclk input 11 the transmit serial incoming clock (tsiclk) provides timing for updating the bit serial outgoing stream when sts-1 mode is selected. tsiclk is nominally a 51.84 mhz, 50% duty cycle clock. tsout is updated on the rising edge of tsiclk. the tsiclk input has an integral pull down resistor. the device may be configured to use the txci+/- inputs as the serial clock. txci+ txci- pecl input 28 27 the transmit differential clock inputs (txci+, txci-) provide timing for updating the bit serial outgoing stream. txci+/- is nominally a 155.52 mhz or 51.84 mhz, 50% duty cycle clock. the tsiclk is the default clock for the 51.84 mbit/s data rate.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 20 pin name pin type pin no. function tin[7] tin[6] tin[5] tin[4] tin[3] tin[2] tin[1] tin[0] input 143 144 145 146 147 148 149 150 the transmit incoming bus, (tin[7:0]), carries an sts-1 or sts-3/stm-1 stream in byte serial format. tin[7] is the most significant bit (corresponding to bit 1 of each serial pcm word, the first bit transmitted). tin[0] is the least significant bit (corresponding to bit 8 of each serial pcm word). tin[7:0] is sampled on the rising edge of ticlk. tifp/ input 142 the active high transmit incoming framing position (tifp/tc1j1v1) signal indicates the frame alignment for incoming streams. when register mode select bit c1en is logic 0, a high level on tifp marks the byte immediately following the z0 bytes in the transmit sts-1 or sts-3 (stm-1) stream, tin[7:0]. tc1j1v1 when register mode select bit c1en is logic 1, a high level on tifp marks the first j0 byte in the transmit sts-1 or sts-3 (stm-1) stream, tin[7:0]. tifp/tc1j1v1 is sampled on the rising edge of ticlk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 21 pin name pin type pin no. function tdis input 151 the active high transmit disable (tdis) signal selectively disables overwriting the sts-1 or sts-3 (stm-1) byte serial stream with the corresponding overhead byte. tdis is sampled on the rising edge of ticlk. tdis takes precedence over the ttohen and ttoh inputs. in general, the value on tin[7:0] passes through transparently if tdis is high. three exceptions exist: 1.) bits 6 to 8 of the k2 byte may be overwritten by a active rdi indication ("110") regardless of the state of tdis. 2.) if tdis is high during the section bip byte (b1), the tin[7:0] value becomes an error mask for the generated section bip. 3.) if tdis is high during the line bip bytes (b2), and the db2 bit in the tlop control register is logic 0, the tin[7:0] value becomes an error mask for the generated line bip. ttoh input 155 the transmit transport overhead bus (ttoh) contains the transport overhead bytes (a1, a2, j0, z0, e1, f1, d1-d3, h3, k1, k2, d4-d12, z1, z2, and e2) and error masks (h1, h2, b1, and b2) which may be inserted, or used to insert bit interleaved parity errors or payload pointer bit errors into the overhead byte positions in the outgoing stream. insertion is controlled by the ttohen input. ttoh is sampled on the rising edge of ttohclk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 22 pin name pin type pin no. function ttohfp output 156 the transmit transport overhead frame position (ttohfp) signal is used to locate the individual transport overhead bits in the transport overhead bus, ttoh. ttohfp is set high while bit 1 (the most significant bit) of the first framing byte (a1) is expected in the incoming stream. ttohfp is updated on the falling edge of ttohclk. ttohclk output 153 the transmit transport overhead clock (ttohclk) is nominally a 5.184 mhz (1.728 mhz for sts-1) clock that provides timing for upstream circuitry that sources the transport overhead, ttoh. ttohclk is a gapped 6.48 mhz clock when accessing the transport overhead of sts-3/stm-1 streams. ttohclk is a gapped 2.16 mhz clock when accessing the transport overhead of an sts-1 stream.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 23 pin name pin type pin no. function ttohen input 152 the transmit transport overhead insert enable (ttohen) signal controls the source of the transport overhead data which is inserted in the transmit stream. while ttohen is high during the most significant bit of a ttoh byte (and tdis is low), values sampled on the ttoh input are inserted into the corresponding transport overhead bit positions (for the a1, a2, j0, z0, e1, f1, d1-d3, h3, k1, k2, d4-d12, z1, z2, and e2 bytes). while ttohen is low during the most significant bit of a ttoh byte, the default values are inserted into these transport overhead byte positions. a high level on ttohen during most significant bit of ttoh for the h1, h2, b1, or b2 bytes enables an error mask. while the error mask is enabled, a high level on ttoh causes the corresponding h1, h2, b1 or b2 bit positions to be inverted. when the section trace enable (sten) bit is a logic 1, the j0 byte contents are sourced from the section trace buffer, regardless of the state of ttohen. a low level on ttoh allows the corresponding bit positions to pass through the stxc uncorrupted. ttohen is sampled on the rising edge of ttohclk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 24 pin name pin type pin no. function trdi/ input 10 the active high transmit far end receive failure (trdi) signal controls the insertion of a far end receive failure indication in the outgoing stream when the ring control port is disabled. when trdi is set high, bits 6, 7, and 8 of the k2 byte are set to the pattern 110. line rdi may also be inserted using the rdi bit in the tlop control register, or upon detection of loss of signal, loss of frame, or line ais in the receive stream, using the autordi bit in the master control/enable register. the trdi input takes precedence over the ttoh and ttohen inputs. trdi is sampled on the rising edge of ticlk. trcpfp the transmit ring control port frame position (trcpfp) signal identifies bit positions in the transmit ring control port data (trcpdat) when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the master control register). trcpfp is high during the filtered k1, k2 bit positions, the change of aps value bit position, the protection switch byte failure bit position, and the send ais and send rdi bit positions in the trcpdat stream. trcpfp is normally connected to the rrcpfp output of a mate stxc in ring-based add-drop multiplexer applications. trcpfp is sampled on the rising edge of trcpclk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 25 pin name pin type pin no. function tlais/ input 9 the active high transmit line alarm indication signal (tlais) controls the insertion of line ais in the outgoing stream when the ring control port is disabled. when tlais is set high, the complete frame (except the section overhead or regenerator section) is overwritten with the all ones pattern (before scrambling). the tlais input takes precedence over the ttoh and ttohen inputs. tlais is sampled on the rising edge of ticlk. trcpdat the transmit ring control port data (trcpdat) signal contains the transmit ring control port data stream when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the master control register). the transmit ring control port data consists of the filtered k1, k2 byte values, the change of aps value bit position, the protection switch byte failure status bit position, the send ais and send rdi bit positions, and the line rei bit positions. trcpdat is normally connected to the rrcpdat output of a mate stxc in ring- based add-drop multiplexer applications. trcpdat is sampled on the rising edge of trcpclk. tsdclk output 6 the transmit section dcc clock (tsdclk) is a 192 khz clock used to sample the tsd input. tsdclk is generated by gapping a 216 khz clock. tsd input 7 the transmit section dcc (tsd) signal contains the section data communications channel (d1, d2, d3) inserted into the outgoing stream. the ttohen input takes precedence over tsd. tsd is sampled on the rising edge of tsdclk.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 26 pin name pin type pin no. function towclk output 3 the transmit order wire clock (towclk) is a 64 khz clock used to sample the tsow, tsuc, and tlow inputs. towclk is generated by gapping a 72 khz clock. tsow input 5 the transmit section order wire (tsow) signal contains the section order wire channel (e1) inserted into the outgoing stream. the ttohen input takes precedence over tsow. tsow is sampled on the rising edge of towclk. tsuc input 4 the transmit section user channel (tsuc) signal contains the section user channel (f1) inserted into the outgoing stream. the ttohen input takes precedence over tsuc. tsuc is sampled on the rising edge of towclk. tlow input 160 the transmit line order wire (tlow) signal contains the line order wire channel (e2) inserted into the outgoing stream. the ttohen input takes precedence over tlow. tlow is updated on the rising edge of towclk. tldclk output 1 the transmit line dcc clock (tldclk) is a 576 khz clock used to sample the tld input. tldclk is generated by gapping a 2.16 mhz clock. tld input 2 the transmit line dcc (tld) signal contains the line data communications channel (d4 - d12) inserted into the outgoing stream. the ttohen input takes precedence over tld. tld is sampled on the rising edge of tldclk. tapsclk output 157 the transmit automatic protection switch channel clock (tapsclk) is a 128 khz clock used to sample the taps input. tapsclk is generated by gapping a 144 khz clock.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 27 pin name pin type pin no. function taps input 158 the transmit automatic protection switch channel (taps) signal carries the automatic protection switch channel (k1, k2) inserted into the outgoing stream. the ttohen input takes precedence over taps. taps is sampled on the rising edge of tapsclk. tout[7] tout[6] tout[5] tout[4] tout[3] tout[2] tout[1] tout[0] output output output output output output output output 39 38 37 36 33 32 31 30 the transmit outgoing stream, (tout[7:0]), carries the scrambled sts-1, or sts-3/stm-1 stream. tout[7] is the most significant bit (corresponding to bit 1 of each serial pcm word, the first bit transmitted). tout[0] is the least significant bit (corresponding to bit 8 of each serial pcm word). tout[7:0] is updated on the rising edge of ticlk. tsout output 29 the transmit serial outgoing stream, (tsout), contains the scrambled stream in bit serial format when serial sts-1 mode is selected. tsout is updated on the rising edge of tsiclk or txci+/-. txd+ txd- pecl output 22 23 the transmit differential data/positive pulse outputs (txd+, txd-) contain the scrambled stream in bit serial format when serial mode is selected. txd+/- is updated on the falling edge of txco+/-. txco+ txco- pecl output 16 15 the transmit differential clock/negative pulse outputs (txco+, and txco-) contain transmit output clock. txco+/- is a buffered version of txci+/-. txd+/- is updated on the falling edge of txco+/-.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 28 pin name pin type pin no. function tofp output 40 the active high transmit outgoing frame position (tofp) signal is asserted once per frame in the byte position immediately following the z0 bytes in the tout[7:0] stream. tofp is also used to mark the alignment of the tsuc, tsow, tlow, and taps bit streams. tofp is updated on the rising edge of ticlk. scpo[5] output 93 the control output (scpo[5]) is used to control an auxiliary device when the rdpen bit in the mode select register is set to logic 0. the signal level on this output corresponds to the bit value contained in the output port register. rdp the receive parity (rdp) signal indicates the parity of the receive bus when the rdpen bit in the mode select register is set to logic 1. the receive data bus (rout[7:0]]) is always included in the parity calculation. internal register bits in the mode select register control the inclusion of rofp in the parity calculation, and the sense (even/odd) of the parity. rdp is updated on the rising edge of riclk. scpo[4] scpo[3] scpo[2] scpo[1] scpo[0] output output output output output 94 95 96 97 98 the control port (scpo[4:0]) together with scpo[5] provides six drive points for controlling auxiliary devices. the signal levels on this output port correspond to the bit values contained in the output port register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 29 pin name pin type pin no. function scpi[3]/ input 89 the status input (scpi[3]) is used to monitor the operation of an auxiliary device when the enh bit in the mode select register is set to logic 0. an interrupt may be generated when state changes are detected in scpi[3]. state changes and the real-time signal levels on this signal are available in the input port status/value register. tdp the transmit parity (tdp) signal indicates the parity of the transmit bus when the enh bit in the mode select register is set to logic 1. the transmit data bus (tin[7:0]) is always included in the parity calculation. internal register bits in the mode select register control the inclusion of frame pulse (tifp/tc1j1) and payload active signal (tpl) in the parity calculation, and the sense (even/odd) of the parity. tdp is sampled on the rising edge of ticlk. scpi[3]/tdp contains an internal pull-down resistor.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 30 pin name pin type pin no. function scpi[2]/ input 90 the status input (scpi[2]) is used to monitor the operation of an auxiliary device when either the c1en or the enh bits in the mode select register are set to logic 0. an interrupt may be generated when state changes are detected in scpi[2]. state changes and the real-time signal levels on this signal are available in the input port status/value register. tpl the transmit payload (tpl) marks when tin[7:0] is carrying a payload byte when both the c1en and enh bits in the mode select register are set to logic 1. it is set high during path overhead and payload bytes and low during transport overhead bytes. tpl is set high during the h3 byte to indicate a negative pointer justification event and set low during the byte following h3 to indicate a positive pointer justification event. the tpl signal is optionally used in the parity calculation of the transmit bus. the transmit data bus (tin[7:0]) is always included in the parity calculation. internal register bits in the mode select register control the inclusion of frame pulse (tifp) and payload active signal (tpl) in the parity calculation, and the sense (even/odd) of the parity. scpi[2]/tpl is sampled on the rising edge of ticlk. scpi[2]/tpl contains an internal pull- down resistor. scpi[1] scpi[0] input input 91 92 the status port (scpi[1:0]) together with scpi[3:2] is used to monitor the operation of auxiliary devices. an interrupt may be generated when state changes are detected in the monitored signals. state changes and the real-time signal levels on this port are available in the input port status/value register. each of the inputs contains an internal pull-down resistor.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 31 pin name pin type pin no. function intb output 99 the active low, open drain interrupt (intb) signal is set when an event is detected on one of the stxc maskable interrupt sources. a[6] a[5] a[4] a[3] a[2] a[1] a[0] input 114 115 116 117 118 119 120 the address bus (a[6:0]) selects specific registers during accesses. ale input 121 the address latch enable (ale) signal latches the address bus (a[6:0]) when low. this allows the stxc to be interfaced to a multiplexed address/data bus. the address latches are transparent when ale is high. the ale input has an integral pull up resistor. mbeb input 122 the active low motorola bus enable (mbeb) signal configures the stxc for motorola bus mode where the rdb/e signal functions as e, and the wrb/rwb signal functions as rwb. when mbeb is high, the stxc is configured for intel bus mode where the rdb/e signal functions as rdb. the mbeb input has an integral pull up resistor. csb input 111 the active low chip select (csb) signal is asserted during all register accesses.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 32 pin name pin type pin no. function d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] i/o 100 101 104 105 106 107 108 109 the bidirectional data bus, d[7:0], is used during stxc read and write accesses. rdb/ input 113 the active low read enable (rdb) signal is low during a stxc read access. the stxc drives the d[7:0] bus with the addressed register's contents while rdb and csb are low. e the active high external access signal (e) is set high during stxc register access while in motorola bus mode. wrb/ input 112 the active low write strobe (wrb) signal is low during a stxc write access. the d[7:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. rwb the read/write select signal (rwb) selects between stxc register read and write accesses while in motorola bus mode. the stxc drives the data bus d[7:0] with the contents of the addressed register while csb is low and rwb and e are high. the contents of d[7:0] are clocked into the addressed register on the falling e edge while csb and rwb are low. rstb input 110 the active low reset (rstb) signal is low to provide an asynchronous reset to the stxc. this schmitt triggered pin contains an internal pull up resistor.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 33 pin name pin type pin no. function vddi[0] vddi[1] vddi[2] power power power 45 76 139 core power pins (vddi[2:0]). these pins must be connected to a common, well decoupled +5 vdc supply together with the vddo[4:0] pins. vssi[0] vssi[1] vssi[2] gnd gnd gnd 50 75 138 core ground pins (vssi[2:0]). these pins must be connected to a common ground together with the vsso[6:0] pins. vddo[0] vddo[1] vddo[2] vddo[3] vddo[4] vddo[5] vddo[6] vddo[7] power power power power power power power power 35 64 74 86 103 130 137 154 pad ring power pins (vddo[4:0]). these pins must be connected to a common, well decoupled +5 vdc supply together with the vddi[2:0] pins. care must be taken to avoid coupling noise induced on the vddo pins into the vddi pins. vsso[0] vsso[1] vsso[2] vsso[3] vsso[4] vsso[5] vsso[6] vsso[7] gnd gnd gnd gnd gnd gnd gnd gnd 34 65 77 85 102 129 136 159 pad ring ground pins (vsso[6:0]). these pins must be connected to a common ground together with the vssi[2:0] pins. vt1 input 13 the transmit pecl logic high reference (vt1) pin must be connected to gnd.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 34 pin name pin type pin no. function vt2 input 25 the transmit pecl logic low reference (vt2) pin is used to control the logic low voltage level of the output pecl pins, txco+/- and txd+/-. vt2 is engineered to sit at tavd4 - 2.0 volts. vt2 should be connected to tavd4 through a reference resistor. the pecl outputs have been designed for optimum performance in a 50 w transmission line environment. under these conditions, the reference resistor value is recommended to be 630 w , 1%. additional details are provided in the application examples section. tav d 1 tav d 2 tav d 3 power 14 18 20 the power (tavd1, tavd2, tavd3) pins for the transmit pecl driver pads. these pins should be connected to the pecl driver supply (nominally vdd). tavd4 reference 26 the reference (tavd4) pin for the transmit pecl circuitry. tavd4 should be connected to the transmit analog reference supply. tavs1 tavs2 tavs3 tavs4 ground 17 19 21 24 the ground (tavs1, tavs2, tavs3, tavs4) pins for the transmit pecl pads. these pins should be connected to gnd. ravd reference 60 the reference pin for the receive pecl circuitry. ravd should be connected to the receive analog reference supply. ravs ground 61 the ground (ravs) pin for the receive pecl pads. ravs should be connected to gnd. notes on pin description: 1. vddi and vssi are the +5 v and ground connections, respectively, for the core circuitry of the device. vddo and vsso are the +5 v and ground connections, respectively, for the pad ring circuitry of the device. these
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 35 power supply connections must all be utilized and must all connect to a common +5 v or ground rail, as appropriate. there is no low impedance connection within the stxc between the core and pad ring supply rails. failure to properly make these connections may result in improper operation or damage to the device. 2. inputs rstb, mbeb and ale have internal pull-up resistors. 3. inputs rsiclk, rsin, tsiclk and scpi[3:0] have internal pull-down resistors. 4. all stxc inputs and bidirectionals present minimum capacitive loading and operate at ttl logic levels except for the txci+, txci-, rxc+, rxc-, rxd+, and rxd- differential inputs which operate at pseudo ecl (pecl) logic levels. 5. most stxc digital outputs and bidirectionals have 4 ma drive capability, except the griclk and gticlk outputs which have 8 ma drive capability. all 4 ma and 8 ma outputs are slew rate limited, except tsout. differential outputs txco+, txco-, txd+, txd- operate at pseudo ecl (pecl) logic levels. 6. when receive bit serial mode is enabled (rser = 1), griclk must be shorted to riclk. the external capacitance must not exceed 30 pf. 7. when transmit bit serial mode is enabled (tser = 1), gticlk must be shorted to ticlk. the external capacitance must not exceed 30 pf.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 36 9 functional description 9.1 serial to parallel converter the serial to parallel converter (sipo) block provides the first stage of digital processing of the receive incoming sts-1 or sts-3 bit serial data stream. the byte alignment in the incoming stream is determined by searching for the 16 bit frame alignment signal (a1, a2) for sts-1 mode, or the 48 bit frame alignment signal (a1, a1, a1, a2, a2, a2) for sts-3 mode. the bit serial stream (rsin, or rxd+/-) is converted from serial to parallel format in accordance with the determined byte alignment. the bit serial input clock (rsiclk, or rxc+/-) is divided by eight to produce the griclk output. griclk must be connected externally to riclk when processing a bit serial stream. both ttl and pecl levels may be used at 51.84 mbit/s, but only the pecl inputs are available at 155.22 mbit/s. 9.2 receive section overhead processor the receive section overhead processor (rsop) block processes the section overhead (regenerator section) of the receive incoming stream. it can be configured to process an sts-1, or sts-3/stm-1 data stream. the rsop block optionally descrambles the received data and extracts the data communication channel, order wire channel and user channel from the section overhead, and provides them as lower rate bit serial outputs (rsd, rsow, rsuc) together with associated clock signals (rsdclk, and rowclk). the complete descrambled sonet/sdh data stream is output by the stxc in byte serial format. line alarm indication signal is inserted in the byte serial output data stream using input rlais or, optionally, automatically when loss-of-frame, section trace or loss-of-signal events occur. the automatic insertion of ais is controlled by the autorais bit in the ring control register. out-of-frame (oof), loss-of-frame (lof), and loss-of-signal (los) state outputs are provided and section level bit-interleaved parity errors are accumulated. a section bip-8 error clock is also provided (b1e). a maskable interrupt is activated by state transitions on the oof, lof, or los outputs, or by a single b1 error event. microprocessor readable registers are provided that allow accumulated b1 errors to be read out at intervals of up to one second duration. the rsop block frames to the data stream by operating with an upstream pattern detector (the serial to parallel converter block; or an external serial to
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 37 parallel converter) that searches for occurrences of the framing pattern (a1, a2) in the bit serial data stream. once the external serial to parallel converter has found byte-alignment, the rsop block monitors for the next occurrence of the framing pattern 125s later. the block declares frame alignment when either all a1 and a2 bytes are seen error-free or when only the first a1 byte and the first four bits of the a2 byte are seen error-free. depending upon the operating mode, the first algorithm examines 2 bytes (a1,a2) in sts-1 mode, or 6 bytes (a1a1a1,a2a2a2) in sts-3/stm-1 mode. the second algorithm examines only the first occurrence of a1 and the first four bits of the first occurrence of a2 in the sequence, regardless of the operating mode. once in frame, the rsop block monitors the framing pattern sequence and declares oof when one or more bit errors in each framing pattern are detected for four consecutive frames. again, depending upon the operating mode selected the first algorithm examines all 2, or 6 framing bytes for bit errors each frame, while the second algorithm examines only the a1 byte and the first four bits of the a2 byte (i.e. 12 bits total) during each frame. the performance of these framing algorithms in the presence of bit errors and random data is robust. when looking for frame alignment the performance of each algorithm is dominated by the alignment algorithm used in the serial to parallel converter. assuming that the sipo block is used, the probability of falsely framing to random data is less than 0.00001% for either algorithm. once in frame alignment, the stxc continuously monitors the framing pattern. when the incoming stream contains a 10 -3 ber, the first algorithm provides a mean time between oof occurrences of 33 minutes in sts-1 mode and 26 seconds in sts-3/stm-1 mode. the second algorithm provides a mean time between oof occurrences of 103 minutes, regardless of operating mode. the rsop block provides descrambled data and frame alignment indication signals for use by the receive line overhead processor. 9.3 receive line overhead processor the receive line overhead processor block (rlop) processes the line overhead (multiplexer section) of a received sonet/sdh data stream. it can be configured to process an sts-1, or an sts-3/stm-1 stream. the sonet frame alignment is indicated by the receive section overhead processor. the rlop extracts the line data communication channel, line order wire channel and automatic protection switch channel from the line overhead, and provides them as lower rate bit serial outputs (rld, rlow, raps) together with associated clock signals (rldclk, rowclk, rapsclk). line alarm indication signal is declared (lais is set high) when the bit pattern 111 is
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 38 observed in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. line ais is removed when any pattern other than 111 is observed for three or five consecutive frames. line far end receive failure is declared (rdi is set high) when the bit pattern 110 is observed in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. line rdi is removed when any pattern other than 110 is observed for three or five consecutive frames. the automatic protection switch bytes (k1, k2) are also extracted into the receive k1 register and the receive k2 register. the bytes are filtered for three frames before being written to these registers. a protection switching byte failure alarm is declared when twelve successive frames have been received, where no three consecutive frames contain identical k1 bytes. the protection switching byte failure alarm is removed upon detection of three consecutive frames containing identical k1 bytes. the detection of invalid aps codes is done in software by polling the receive k1/k2 registers the line level bit-interleaved parity (b2) is computed, and compared to the received b2 bytes. line bip-8 errors are accumulated in an internal counter. registers are provided that allow accumulated line bip-8 errors to be read out at intervals of up to one second duration. a line bip-8 error clock is also provided (b2e). signal fail (sf) and signal degrade (sd) threshold crossing alarms are detected and indicated using internal register bits. the bit error rates associated with the sf and sd alarms are programmable over a range of 10 -3 to 10 -9 . the bit error rate monitor (berm) circuit block extracts the automatic protection switch (aps) bytes (k1 and k2), extracts the synchronization status byte (z1), and processes the line bip-8 (b2) error signal. a protection switching byte failure alarm is declared when twelve successive frames have been received, where no three consecutive frames contain identical k1 bytes. the protection switching byte failure alarm is removed upon detection of three consecutive frames containing identical k1 bytes. the detection of invalid aps codes is done in software by polling the aps k1 register and the aps k2 register. the received line bip-8/24 error detection code (b2) byte is based on the line overhead and synchronous payload envelope of the receive stream. the line bip code is a bit interleaved parity calculation using even parity, and the calculated bip code is compared with the bip code extracted from the b2 bytes of the following frame. any differences indicate that a line layer bit error has occurred. up to 192000 (24 bip/frame x 8000 frames/seconde) bit errors can be detected per second for sts-3 rate and 64000 (8 bip/frame x 8000 frames/seconde) for sts-1 rate.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 39 the line level far end block error byte (m1) is extracted and accumulated in an internal counter. registers are provided that allow accumulated line rei events to be read out at intervals of up to one second duration. bits 2 through 8 of the z2 byte are used for the line rei function. for sts-1 streams, the line rei byte has 9 legal values (namely 00h - 08h) representing 0 to 8 rei events. for sts- 3 streams, the line rei byte has 25 legal values (namely 00h - 18h) representing 0 to 24 rei events. illegal z2 values are interpreted as zero errors. an interrupt output is provided that may be activated by declaration or removal of line ais, line rdi, protection switching byte failure alarm, a change of aps code value, a single b2 error event, or a single line rei event. each interrupt source is individually maskable. 9.4 receive transport overhead access the receive transport overhead access block (rtoh) extracts the entire receive transport overhead on the rtoh, along with the 5.184 mhz or 1.728 mhz transport overhead clock, rtohclk, and the transport overhead frame position, rtohfp, allowing identification of the bit positions in the transport overhead stream. 9.5 ring control port the transmit and receive ring control ports provide bit serial access to section and line layer alarm and maintenance signal status and control. these ports are useful in ring-based add drop multiplexer applications where alarm status and maintenance signal insertion control must be passed between separate stxcs (possibly residing on separate cards). each ring control port consists of three signals: clock, data and frame position. it is intended that the clock, data and frame position outputs of the receive ring control port are connected directly to the clock, data and frame position inputs of the transmit ring control port on the mate stxc. the alarm status and maintenance signal control information that is passed on the ring control ports consists of filtered aps (k1 and k2) byte values change of filtered aps byte value status protection switch byte failure alarm status change of protection switch byte failure alarm status insert the line rdi maintenance signal in the mate stxc
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 40 insert the line ais maintenance signal in the mate stxc insert line rei information in the mate stxc. the same aps byte values must be seen for three consecutive frames before being shifted out on the receive ring control port. the change of filtered aps byte value status is high for one frame when a new, filtered aps value is shifted out. the protection switch byte failure alarm bit position is high when twelve consecutive frames, where no three consecutive frames contain identical k1 bytes have been received. the bit position is set low when three consecutive frames containing identical k1 bytes have been received. the change of protection switch byte failure alarm status bit position is set high for one frame when the alarm state changes. the insert line rdi bit position is set high under register control, or when loss of signal, loss of frame, or line ais alarms are declared. the insert line ais bit position is set high under register control only. the insert line rei bit positions are high for one bit position for each detected b2 bit error. up to 24 reis may be indicated per frame for an sts-3/stm-1 signal. 9.6 transmit transport overhead access the transmit transport overhead access block (ttoh) allows the complete transport overhead to be inserted using the ttoh, along with the 5.184 mhz or 1.728 mhz transport overhead clock, ttohclk, and the transport overhead frame position, ttohfp. the transport overhead enable signal, ttohen, controls the insertion of transport overhead from ttoh. the stxc also supports upstream insertion of the line overhead using the tdis input. tdis is used to disable the insertion of transport overhead either from the ttoh bus, or from the individual channels (tsd, tsow, tsuc, tld, taps, and tlow). 9.7 transmit line overhead processor the transmit line overhead processor block (tlop) processes the line overhead of the transmit stream. it can be configured to process an sts-1, or sts-3 (stm-1) stream that is presented in byte serial format at the rate of 6.48 mbyte/s, or 19.44 mbyte/s respectively. the tlop optionally inserts the line data communication channel, the line order wire channel, and the automatic protection switch channel into the line overhead of the transmit stream. these line overhead channels are separately fed to the
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 41 tlop as bit serial inputs (tld, tlow, and taps). the tlop provides the bit serial clock for each line overhead channel (tldclk, towclk, tapsclk). line rdi may be inserted in the transmit stream under the control of an external input (trdi), or a writeable register. the autordi bit in the ring control register controls the immediate insertion of line rdi upon detection of line ais in the received sonet/sdh stream. line rei may be inserted automatically in the sonet/sdh stream under the control of the autorei bit in the ring control register. receive b2 errors are accumulated and optionally inserted automatically in bits 2 to 8 of the third z2 byte of the transmit stream (for sts-3/stm-1 modes), or in bits 2 to 8 of the z2 byte of the transmit stream for sts-1 mode. up to 8 or 24 errors may be inserted per frame for sts-1 or sts-3/stm-1 modes, respectively. the line bip (b2) error detection code for the transmit stream is calculated by the tlop and is inserted into the line overhead. errors may be inserted in the b2 code for diagnostic purposes. a byte serial stream, along with a frame position indicator is passed to the transmit section overhead processor. 9.8 transmit section overhead processor the transmit section overhead processor (tsop) block processes the section overhead of the transmit stream. it can be configured to process an sts-1, or an sts-3/stm-1 stream that is presented in byte serial format at 6.48 mbyte/s, or 19.44 mbyte/s respectively. the tsop accepts an unscrambled stream in byte serial format from the transmit line overhead processor. it optionally inserts the section data communication channel, the order wire channel, and the user channel into the section overhead (regenerator section) of the stream. these section overhead channels are input to the stxc as bit serial signals (tsd, tsow, and tsuc). the tsop provides the bit serial clock for each section overhead channel (tsdclk, and towclk). the line alarm indication signal may optionally be inserted into the data stream under the control of an external input (tlais), or a microprocessor writeable register. the section bip-8 error detection code (b1) is calculated by the tsop block and is inserted into the section overhead of the transmit stream. errors may be inserted in the b1 code for diagnostic purposes. framing (a1, a2) and identity bytes (j0) are also inserted. finally, the complete transmit stream is scrambled and output by the tsop in byte serial format on outputs tout[7:0].
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 42 the tsop block is intended to operate with a downstream serializer (the parallel to serial converter block; or an external parallel to serial converter) that accepts the transmit stream in byte serial format and serializes it at the appropriate line rate. 9.9 parallel to serial converter the parallel to serial converter (piso) block provides the final stage of digital processing for the transmit data stream. the piso block converts the data stream from parallel to serial format. a generated transmit clock (gticlk) is provided by dividing the incoming transmit line clock (tsiclk, or txc+/-) by eight. gticlk must be externally connected to ticlk when processing a bit serial stream. 9.10 receive section trace buffer the receive portion of the sonet section trace buffer captures the received section trace identifier message (j0 byte) into microprocessor readable registers. it contains two pages of trace message memory. one is designated the capture page and the other the expected page. section trace identifier data bytes from the receive stream are written into the capture page. the expected identifier message is downloaded by the microprocessor into the expected page. on receipt of a trace identifier byte, it is written into next location in the capture page. the received byte is compared with the data from the previous message in the capture page. an identifier message is accepted if it is received unchanged three times, or optionally, five times. the accepted message is then compared with the expected message. if enabled, an interrupt is generated when the accepted message changes from matching to mismatching the expected message and vice versa. if the current message differs from the previous message for eight consecutive messages, the received message is declared unstable. the received message is declared stable when the received message passes the persistency criterion (three or five identical receptions) for being accepted. an interrupt may be optionally generated on entry to and exit from the unstable state. optionally, ais may be inserted in the rout[7:0] bus when the receive message is in the mismatched or unstable state. the length of the section trace identifier message is selectable between 16 bytes and 64 bytes. when programmed for 16 byte messages, the section trace buffer synchronizes to the byte with the most significant bit set to high and places the byte at the first location in the capture page. when programmed for 64 byte messages, the section trace buffer synchronizes to the trailing carriage return (cr = 0dh), line feed (lf = 0ah) sequence and places the next byte at the
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 43 head of the capture page. this enables the section trace message to be appropriately aligned for interpretation by the microprocessor. synchronization may be disabled, in which case, the memory acts as a circular buffer. 9.11 transmit section trace buffer the transmit portion of the sonet section trace buffer sources the section trace identifier message (j0) for the transmit transport overhead access block. the length of the trace message is selectable between 16 bytes and 64 bytes. the section trace buffer contains one page of transmit trace identifier message memory. identifier message data bytes are written by the microprocessor into the message buffer and delivered serially to the transport overhead access block for insertion in the transmit stream. when the microprocessor is updating the transmit page buffer, the buffer may be programmed to transmit null characters to prevent transmission of partial messages. 9.12 microprocessor interface the microprocessor interface block provides the logic required to interface the normal mode and test mode registers within the stxc to a generic microprocessor bus. the normal mode registers are used during normal operation to configure and monitor the stxc while the test mode registers are used to enhance the testability of the stxc.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 44 10 register description table 1 - normal mode register memory map a[6:0] register (enh* bit = logic 0) register (enh* bit = logic 1) 00h master configuration master configuration 01h master control/enable master control/enable 02h master interrupt status master interrupt status 03h master reset and identity master reset and identity 04h tlop control tlop control 05h tlop diagnostic tlop diagnostic 06h transmit k1 transmit k1 07h transmit k2 transmit k2 08h rlop control/status rlop control/status 09h rlop interrupt rlop interrupt 0ah b2 error count #1 b2 error count #1 0bh b2 error count #2 b2 error count #2 0ch b2 error count #3 b2 error count #3 0dh rei error count #1 rei error count #1 0eh rei error count #2 rei error count #2 0fh rei error count #3 rei error count #3 10h rsop control rsop control 11h rsop interrupt status rsop interrupt status 12h b1 error count #1 b1 error count #1 13h b1 error count #2 b1 error count #2 14h output port output port 15h input port interrupt enable input port interrupt enable 16h mode select mode select 17h ring control port ring control port 18h tsop control tsop control
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 45 a[6:0] register (enh* bit = logic 0) register (enh* bit = logic 1) 19h tsop diagnostic tsop diagnostic 1ah transmit z1 transmit z1 1bh receive z1 transmit z0 1ch reserved reserved 1dh receive k1 ais control 1eh receive k2 rdi control 1fh input port status/value input port status/value 20h section trace control rase interrupt enable 21h section trace status rase interrupt status 22h section trace indirect address rase configuration/control 23h section trace indirect data sf accumulation period (lsb) 24h reserved sf accumulation period 25h reserved sf accumulation period (msb) 26h reserved sf saturation threshold (lsb) 27h reserved sf saturation threshold (msb) 28h section trace ais insertion sf declaring threshold (lsb) 29h reserved sf declaring threshold (msb) 2ah reserved sf clearing threshold (lsb) 2bh reserved sf clearing threshold (msb) 2ch reserved sd accumulation period (lsb) 2dh reserved sd accumulation period 2eh reserved sd accumulation period (msb) 2fh reserved sd saturation threshold (lsb) 30h reserved sd saturation threshold (msb) 31h reserved sd declaring threshold (lsb) 32h reserved sd declaring threshold (msb) 33h reserved sd clearing threshold (lsb) 34h reserved sd clearing threshold (msb)
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 46 a[6:0] register (enh* bit = logic 0) register (enh* bit = logic 1) 35h reserved receive k1 36h reserved receive k2 37h reserved receive z1 38h reserved section trace control 39h reserved section trace status 3ah reserved section trace indirect address 3bh reserved section trace indirect data 3ch- 3fh reserved reserved 40h-7fh reserved for stxc test reserved for stxc test * the enh bit is contained in the mode select register (addr 16h). notes on register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the stxc to determine the programming state of the device. 3. writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect stxc operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the stxc operates as intended, reserved register bits must only be written with logic zero. similarly, writing to reserved registers should be avoided.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 47 address 00h: master configuration bit type function default bit 7 r/w sten 0 bit 6 r/w tmode 1 bit 5 r/w fpos 0 bit 4 r/w lle 0 bit 3 r/w dle 0 bit 2 r/w rxsel 0 bit 1 r/w lte 0 bit 0 r/w rmode 1 rmode: the rmode bus selects the operating mode of the receive overhead processor, as follows: rmode mode 0sts-1 1 sts-3 (stm-1) lt e : the lte bit selects the source of timing for the transmit section of the stxc. loop time operation can only be activated while the receive and transmit bit serial interfaces are selected. when lte is a logic zero, the transmitter timing is derived from inputs txci+ and txci- or, optionally, from input tsiclk when sts-1 mode is selected. when lte is a logic one, and the bit serial interface is selected (tser and rser are both tied high), the transmitter timing is derived from the receiver inputs rxci+ and rxci- or, optionally, from input rsiclk when sts-1 bit serial mode is selected. loop timed operation is not supported when the byte serial interface is selected (either tser or rser is tied low). rxsel: the rxsel bit only has effect when the rser input is high and the rmode bit is a logic zero. if rxsel is a logic zero in this situation, the 51.84 mbit/s
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 48 serial stream and associated clock are expected as ttl compatible signals on the rsin and rsiclk inputs, respectively. if rxsel is a logic one, the 51.84 mbit/s serial stream and associated clock are expected as pecl compatible signals on the rxd+/- and rxc+/- inputs, respectively. dle: the dle bit enables the stxc diagnostic loopback. diagnostic loopback may only be activated while the bit serial interface is selected (tser and rser are both tied high). when dle is a logic one, the transmit stream is connected to the receive stream. lle: the lle bit enables the stxc line loopback. line loopback may only be activated while the bit serial interface is selected (tser and rser are both tied high). when lle is a logic one, rxd+, rxd-, rxc+, rxc-, and rsin are connected internally to txd+, txd-, txco+, txco-, and tsout respectively. fpos: when the byte serial receive sts-3 mode is selected, the fpos bit controls receive interface of the stxc. when fpos is a logic zero, the receive incoming frame position (rifp) is expected during the third a2 byte of the receive incoming stream (rin[7:0]). when fpos is a logic one, the receive incoming frame position is indicated during the byte position immediately following the last z0 byte in the receive incoming stream. in the byte serial receive sts-1 mode, the incoming frame position is indicated during the byte position immediately following the z0 byte in the receive incoming stream regardless of the state of fpos. tmode: the tmode bus selects the operating mode of the transmit overhead processor as follows: tmode mode 0sts-1 1 sts-3 (stm-1) sten: the sten bit controls whether the section trace message stored in the section trace buffer is inserted in the transmit stream. when sten is a logic
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 49 one, the message in the section trace buffer is inserted in the transmit stream. when sten is a logic zero, the z0 byte contents are supplied by the tsop block or via the ttoh input.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 50 address 01h: master control/enable bit type function default bit 7 r/w rcp 0 bit 6 r/w z1e/z0ins 0 bit 5 r/w psbfe/tdpe 0 bit 4 r/w coapse/rasee 0 bit 3 r/w tclksel 0 bit 2 r/w rsope 0 bit 1 r/w stbe 0 bit 0 r/w rlope 0 rlope: the rlop interrupt enable is an interrupt mask for events detected by the receive line overhead processor. when rlope is a logic one, an interrupt is generated when line layer events are detected, provided the associated enable in the rlop interrupt enable and status register is set. stbe: the section trace buffer interrupt enable is an interrupt mask for events detected by the receive section trace buffer. when stbe is a logic one, an interrupt is generated when section trace events are detected by the section trace buffer. rsope: the rsop interrupt enable is an interrupt mask for events detected by the receive section overhead processor. when rsope is a logic one, an interrupt is generated when section layer events are detected, provided the associated enable in the rsop control register is set. tclksel: the tclksel bit only has effect when the tser input is high and the tmode bit is a logic zero. if tclksel is a logic zero in this situation, ttl compatible tsiclk input is the source of the 51.84 mhz transmit serial clock. if tclksel is a logic one, the pecl compatible txci+/- inputs are the source of the 51.84 mhz transmit serial clock.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 51 coapse/rasee: the change of aps byte interrupt enable (coapse) is an interrupt mask for events detected by the receive aps processor. when the enh bit in the mode select register is a logic 0, coapse set to a logic one enables an interrupt to be generated when a new k1/k2 code value has been extracted into the receive k1/k2 registers. the rase interrupt enable (rasee) is an interrupt mask for events detected by the receive aps and synchronization extractor. when the enh bit in the mode select register is a logic 1, rasee set to a logic one enables an interrupt to be generated when the aps status changes, aps alarm or a threshold crossing, provided the associated enable in the rase interrupt enable register is set. psbfe/tdpe: the change of protection switch byte failure alarm interrupt enable (psbfe) is an interrupt mask for events detected by the receive aps processor. when psbfe is a logic one, and the enh bit in the mode select register is a logic 0, an interrupt is generated upon a change in the protection switch byte failure alarm state. the transmit parity error interrupt enable (tdpe) is an interrupt mask for parity errors detected on the transmit bus. when tdpe is a logic one, and the enh bit in the mode select register is logic 1, an interrupt is generated when parity errors are detected on the transmit bus. z1e/z0ins: the change of z1 interrupt enable (z1e) is an interrupt mask for changes in the receive z1 byte value. when z1e is a logic one, and the enh bit in the mode select register is a logic 0, an interrupt is generated when the extracted z1 byte is different from the z1 byte extracted in the previous frame. the z0ins bit controls the values inserted in the transmit z0 bytes when sts-3/stm-1 mode is selected. when z0ins is logic 1, and the enh bit in the mode select register is a logic 0, the value contained in the transmit z0 register is inserted in the two z0 bytes. when z0ins is logic 0, the values 02h and 03h are inserted in z0 byte of 2nd and 3rd sts-1 respectively. note that values inserted using the transmit transport overhead port or the tdis input take priority over z0ins. note also that this bit must be set to logic 0 for the dc1 bit in the tsop control register to function correctly.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 52 rcp: the rcp bit controls the enabling of the receive and transmit ring control ports. when rcp is a logic zero, the ring control ports are disabled, and the los, lais and rdi outputs and the rlais, tlais, and trdi inputs are used to monitor alarm status and control maintenance signal insertion. when rcp is a logic one, the ring control ports are enabled, and alarm status and maintenance signal insertion control is provided by the rrcpclk, rrcpfp, and rrcpdat outputs and the trcpclk, trcpfp, and trcpdat inputs.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 53 address 02h: master interrupt status bit type function default bit 7 r psbfv x bit 6 r z1i x bit 5 r psbfi/tdpi x bit 4 r coapsi/rasei x bit 3 unused x bit 2 r rsopi x bit 1 r stbi x bit 0 r rlopi x rlopi: the rlopi bit is set high when one or more of the maskable interrupt sources in the receive line overhead processor has been activated. this register bit remains high until the interrupt is acknowledged by reading the rlop interrupt enable and status register. stbi: the stbi bit is set high when one or more of the maskable interrupt sources in the section trace buffer has been activated. this register bit remains high until the interrupt is acknowledged by reading the section trace interrupt enable and status register. rsopi: the rsopi bit is set high when one or more of the maskable interrupt sources in the receive section overhead processor has been activated. this register bit remains high until the interrupt is acknowledged by reading the rsop interrupt status register. coapsi/rasei: the coapsi bit is set high when a new aps code value has been extracted into the receive k1/k2 registers and the enh bit in the mode select register is a logic 0. the registers are updated when the same new k1/k2 byte values are observed for three consecutive frames. this bit is cleared when the master interrupt status register is read.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 54 the rasei bit is set high when one or more of the maskable interrupt sources in the receive aps and synchronization extractor has been activated and the enh bit in the mode select register is a logic 1. this register bit remains high until the interrupt is acknowledged by reading the rase interrupt status register. psbfi/tdpi: the psbfi bit is set high when the protection switching byte failure alarm is declared or removed and the enh bit in the mode select register is a logic 0. this bit is cleared when the master interrupt status register is read. the tdpi bit is set high when a parity error is detected on the transmit bus and both the enh bit in the mode select register are logic 1. this bit is cleared when the master interrupt status register is read. z1i: the z1i bit is set high when a new z1 byte value has been extracted into the receive z1 register and the enh bit in the mode select register is a logic 0. the register is updated when a z1 byte value is extracted that is different than the z1 byte value extracted in the previous frame. this bit is cleared when the master interrupt status register is read. this bit position is reserved when the enh bit in the mode select register is a logic 1. psbfv: the psbfv bit indicates the protection switching byte failure alarm state when the enh bit in the mode select register is a logic 0. the alarm is declared (psbfv is set high) when twelve successive frames, where no three consecutive frames contain identical k1 bytes, have been received. the alarm is removed (psbfv is set low) when three consecutive frames containing identical k1 bytes have been received. this bit position is reserved when the enh bit in the mode select register is a logic 1.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 55 address 03h: master reset and identity bit type function default bit 7 r/w reset 0 bit 6 r riclka 0 bit 5 r ticlka 0 bit 4 r id[4] 0 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 1 a write to this register initiates a transfer of all performance monitor counter values (b1, b2, and line rei) into holding registers. id[4:0]: the version identification bits id[4:0], are set to the value 01h, representing the version number of the stxc. ticlka: the transmit clock activity monitor is set to a logic one if one or more rising edges are detected on primary input ticlk since the last time this register was read. a logic zero in this bit position indicates tclk is not toggling. riclka: the receive clock activity monitor is set to a logic one if one or more rising edges are detected on primary input riclk since the last time this register was read. a logic zero in this bit position indicates riclk is not toggling. reset: the reset bit allows the stxc to be asychronously reset. the software reset is equivalent to setting the rstb input pin low. when reset is a logic one, the stxc is reset. when reset is a logic zero, the reset is removed. the reset bit must be explicitly set and cleared by writing the corresponding logic value to this register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 56 address 04h: tlop control bit type function default bit 7 r/w db2 0 bit 6 r/w ubt 0 bit 5 r/w apsreg 0 bit 4 r/w dz2 0 bit 3 r/w daps 0 bit 2 r/w ddl 0 bit 1 r/w dow 0 bit 0 r/w rdi 0 rdi: the rdi bit controls the insertion of transmit line remote defect indication (rdi). when rdi is a logic one, line rdi is inserted into the transmit stream. line rdi is inserted by transmitting the code 110 in bit positions 6, 7, and 8 of the k2 byte. line rdi may also be inserted using the trdi input (when the ring control ports are disabled) or using the transmit ring control port (when it is enabled). when rdi is logic zero, bit 6, 7, and 8 of the k2 byte are not modified by the transmit line overhead processor. dow: the dow bit controls the overwriting of the express orderwire byte (e2). when dow is logic one, the value sampled on tin[7:0] during the e2 byte position is passed through the transmit line overhead processor unaltered, as though the tdis input had been sampled high during the e2 byte position in the incoming frame. the upstream insertion of the express orderwire is thus accomplished without the use of the tdis input. note that only the e2 byte position is passed unaltered, the remaining 2 (sts-3/stm-1) undefined byte positions are overwritten with all zeros. this overwriting may be defeated by using the tdis input, or by using the ubt bit in this register. when dow is logic zero, the express order wire source is nominally the tlow input (while tdis and ttohen are both low). ddl: the ddl bit controls the overwriting of the line data communications channel (d4 - d12). when ddl is logic one, the values sampled on tin[7:0] during
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 57 the d4 - d12 byte positions are passed through the transmit line overhead processor unaltered, as though the tdis input had been sampled high during the d4 - d12 byte positions in the incoming frame. the upstream insertion of the line dcc is thus accomplished without the use of the tdis input. note that only the d4 - d12 byte positions are passed unaltered, the remaining 18 (sts-3/stm-1) undefined byte positions are overwritten with all zeros. this overwriting may be defeated by using the tdis input, or by using the ubt bit in this register. when ddl is logic zero, the line dcc source is nominally the tld input (while tdis and ttohen are both low). daps: the daps bit controls the overwriting of the automatic protection switch channel (k1, k2). when daps is logic one, the values sampled on tin[7:0] during the k1 and k2 byte positions are passed through the transmit line overhead processor unaltered, as though the tdis input had been sampled high during the k1 and k2 byte positions in the incoming frame. the upstream insertion of the aps channel is thus accomplished without the use of the tdis input. note that only the k1 and k2 byte positions are passed unaltered, the remaining 4 (sts-3/stm-1) undefined byte positions are overwritten with all zeros. this overwriting may be defeated by using the tdis input, or by using the ubt bit in this register. when daps is logic zero, the aps source is nominally the taps input or the transmit k1/k2 registers (as selected by the apsreg bit in the tlop control register while tdis and ttohen are both low). dz2: the dz2 bit controls the overwriting of the z2 growth byte. when dz2 is logic one, the values sampled on tin[7:0] during the z2 byte position are passed through the transmit line overhead processor unaltered, as though the tdis input had been sampled high during the z2 byte position in the incoming frame. the upstream insertion of the growth bytes is thus accomplished without the use of the tdis input. note that all 3 (sts-3/stm-1) or 1 (sts-1) z2 bytes are passed through unaltered. when dz2 is logic zero, the z2 byte positions are nominally overwritten with the line rei value and all zeros (while tdis and ttohen are both low). apsreg: the apsreg bit selects the source for the transmit aps channel. when apsreg is a logic zero, the transmit aps channel is inserted from the bit serial input taps which is shifted in on the rising edge of tapsclk. when apsreg is a logic one, the transmit aps channel is inserted from the transmit k1 register and the transmit k2 register. the aps bytes may also
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 58 be inserted upstream of the tlop using the tdis or ttohen inputs, or the daps bit in the tlop control register. values inserted using tdis take precedence over the source selected by the apsreg bit. ubt: the ubt bit controls the overwriting of the unused byte positions in the transmit sts-3/stm-1 stream. the unused bytes are contained in the k1, k2, d4-d12, and e2 byte positions of sts-1 #2 and sts-1 #3. when ubt is logic zero, the unused byte position are overwritten with all zeros. when ubt is logic one, the values sampled on tin[7:0] during the unused byte positions are passed through the transmit line overhead processor unaltered, as though the tdis input had been sampled high during the unused byte positions in the incoming frame. db2: the db2 bit controls the insertion of the b2 bytes. when db2 is logic one, the values sampled on tin[7:0] during the b2 byte positions are passed through the transmit line overhead processor unaltered. when db2 is logic zero, the internally calculated bit interleaved parity bytes are inserted in the b2 byte positions.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 59 address 05h: tlop diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r/w db2 0 db2: the db2 bit controls the insertion of bit errors continuously in each of the line bip-8 bytes (b2 bytes). when db2 is set high, each bit of every b2 byte is inverted.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 60 address 06h: transmit k1 bit type function default bit 7 r/w k1[7] 0 bit 6 r/w k1[6] 0 bit 5 r/w k1[5] 0 bit 4 r/w k1[4] 0 bit 3 r/w k1[3] 0 bit 2 r/w k1[2] 0 bit 1 r/w k1[1] 0 bit 0 r/w k1[0] 0 k1[7:0]: the k1[7:0] bits contain the value inserted in the k1 byte when the apsreg bit in the tlop control register is logic one. k1[7] is the most significant bit corresponding to bit 1, the first bit transmitted. k1[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. the bits in this register are double buffered so that register writes do not need to be synchronized to sonet/sdh frame boundaries. the insertion of a new aps code value is initiated by a write to this register. the contents of this register, and the transmit k2 register are inserted in the sonet/sdh stream starting at the next frame boundary. successive writes to this register must be spaced at least two frames (250 s) apart.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 61 address 07h: transmit k2 bit type function default bit 7 r/w k2[7] 0 bit 6 r/w k2[6] 0 bit 5 r/w k2[5] 0 bit 4 r/w k2[4] 0 bit 3 r/w k2[3] 0 bit 2 r/w k2[2] 0 bit 1 r/w k2[1] 0 bit 0 r/w k2[0] 0 k2[7:0]: the k2[7:0] bits contain the value inserted in the k2 byte when the apsreg bit in the tlop control register is logic one. k2[7] is the most significant bit corresponding to bit 1, the first bit transmitted. k2[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. the bits in this register are double buffered so that register writes do not need to be synchronized to sonet/sdh frame boundaries. the insertion of a new aps code value is initiated by a write to the transmit k1 register. a coherent aps code value is ensured by writing the desired k2 aps code value to this register before writing the transmit k1 register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 62 address 08h: rlop control/status bit type function default bit 7 r/w bipword 0 bit 6 r/w allones 0 bit 5 r/w aisdet 0 bit 4 r/w rdidet 0 bit 3 r/w bipwordo 0 bit 2 unused x bit 1 r laisv x bit 0 r rdiv x rdiv: the rdiv bit is set high when line rdi is detected. line rdi is detected when a 110 binary pattern is detected in bits 6, 7, and 8, of the k2 byte for three or five consecutive frames (as selected by the rdidet bit in this register). line rdi is removed when any pattern other than 110 is detected for three or five consecutive frames. this alarm indication is also available on output rdi. laisv: the laisv bit is set high when line ais is detected. line ais is detected when a 111 binary pattern is detected in bits 6, 7, and 8, of the k2 byte for three or five consecutive frames (as selected by the aisdet bit in this register). line ais is removed when any pattern other than 111 is detected for three or five consecutive frames. this alarm indication is also available on output lais. bipwordo: the bipwordo bit controls the indication of b2 errors on the b2e output. when bipwordo is logic one, the b2e output is asserted for once per frame whenever one or more b2 bit errors occur during that frame. when bipwordo is logic zero, the b2e output is asserted once for every b2 bit error that occurs during that frame ( the bipe output can be asserted up to 8xn bipeclk periods, for n=1, or 3). the accumulation of b2 error events functions independently from the b2e output indication, and is controlled by the bipword register bit.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 63 if the autorei register bit is a logic one and the ringen register bit is a logic zero, the number of block errors sent to the far end in the line rei bits equals the number of b2e assertions. if bipwordo is a logic one, bits 2 through 8 of the transmitted z2 byte may only contain 00h and 01h. rdidet: the rdidet bit determines the line rdi alarm detection algorithm. when rdidet is set to logic one, line rdi is declared when a 110 binary pattern is detected in bits 6,7,8 of the k2 byte for three consecutive frames and is cleared when any pattern other than 110 is detected in bits 6, 7, and 8 of the k2 byte for three consecutive frames. when rdidet is set to logic zero, line rdi is declared when a 110 binary pattern is detected in bits 6,7,8 of the k2 byte for five consecutive frames and is cleared when any pattern other than 110 is detected in bits 6, 7, and 8 of the k2 byte for five consecutive frames. aisdet: the aisdet bit determines the line ais alarm detection algorithm. when aisdet is set to logic one, line ais is declared when a 111 binary pattern is detected in bits 6,7,8 of the k2 byte for three consecutive frames and is cleared when any pattern other than 111 is detected in bits 6, 7, and 8 of the k2 byte for three consecutive frames. when aisdet is set to logic zero, line ais is declared when a 111 binary pattern is detected in bits 6,7,8 of the k2 byte for five consecutive frames and is cleared when any pattern other than 111 is detected in bits 6, 7, and 8 of the k2 byte for five consecutive frames. allones: the allones bit controls automatically forcing the rout[7:0] outputs to logical all-ones whenever line ais is detected. when allones is set to logic one, the output bus is forced to logic one immediately when the line ais alarm is declared. when line ais is removed, the outputs are immediately returned to carrying the receive stream. when allones is set to logic zero, the outputs carry the receive stream regardless of the state of the line ais alarm. bipword: the bipword bit controls the accumulation of b2 errors. when bipword is logic one, the b2 error event counter is incremented only once per frame whenever one or more b2 bit errors occur during that frame. when bipword is logic zero, the b2 error event counter is incremented for each b2 bit error that occurs during that frame (the counter can be incremented up to 8xn times per frame, for n=1 or 3).
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 64 address 09h: rlop interrupt enable and status bit type function default bit 7 r/w reie 0 bit 6 r/w bipee 0 bit 5 r/w laise 0 bit 4 r/w rdie 0 bit 3 r reii x bit 2 r bipei x bit 1 r laisi x bit 0 r rdii x rdii: the rdii bit is set high when line rdi is declared or removed. this bit is cleared when the rlop interrupt enable and status register is read. laisi: the laisi bit is set high when line lais is declared or removed. this bit is cleared when the rlop interrupt enable and status register is read. bipei: the bipei bit is set high when a line bip error is detected. this bit is cleared when the rlop interrupt enable and status register is read. rdie: the rdi interrupt enable is an interrupt mask for line rdi. when rdie is a logic one, a line interrupt is generated when line rdi is declared or removed. laise: the lais interrupt enable is an interrupt mask for line ais. when laise is a logic one, a line interrupt is generated when line ais is declared or removed. bipee: the line bip error interrupt enable is an interrupt mask for line bip error events. when bipee is a logic one, a line interrupt is generated when a line bip error (b2) is detected.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 65 reie: the line remote error indication interrupt enable is an interrupt mask for line rei events. when reie is a logic one, a line interrupt is generated when a line rei indication is detected.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 66 address 0ah: b2 error count #1 bit type function default bit 7 r be[7] x bit 6 r be[6] x bit 5 r be[5] x bit 4 r be[4] x bit 3 r be[3] x bit 2 r be[2] x bit 1 r be[1] x bit 0 r be[0] x address 0bh: b2 error count #2 bit type function default bit 7 r be[15] x bit 6 r be[14] x bit 5 r be[13] x bit 4 r be[12] x bit 3 r be[11] x bit 2 r be[10] x bit 1 r be[9] x bit 0 r be[8] x address 0ch: b2 error count #3 bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r be[19] x bit 2 r be[18] x bit 1 r be[17] x bit 0 r be[16] x
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 67 be[19:0]: bits be[19] through be[0] represent the number of line bit-interleaved parity errors that have been detected since the last accumulation interval. the error counters are polled by writing to any of the b2 error count register addresses (0ah, 0bh, or 0ch), or by writing to the master reset and identity register (03h). such a write transfers the internally accumulated error count to the registers within 1s and simultaneously resets the internal counters to begin a new cycle of error accumulation. after the 1s period has elapsed, the b2 error count registers may be read.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 68 address 0dh: rei error count #1 bit type function default bit 7 r fe[7] x bit 6 r fe[6] x bit 5 r fe[5] x bit 4 r fe[4] x bit 3 r fe[3] x bit 2 r fe[2] x bit 1 r fe[1] x bit 0 r fe[0] x address 0eh: rei error count #2 bit type function default bit 7 r fe[15] x bit 6 r fe[14] x bit 5 r fe[13] x bit 4 r fe[12] x bit 3 r fe[11] x bit 2 r fe[10] x bit 1 r fe[9] x bit 0 r fe[8] x address 0fh: rei error count #3 bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r fe[19] x bit 2 r fe[18] x bit 1 r fe[17] x bit 0 r fe[16] x
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 69 fe[19:0]: bits fe[19] through fe[0] represent the number of line remote error indications that have been detected since the last accumulation interval. the error counters are polled by writing to any of the rei error count register addresses (0dh, 0eh, or 0fh), or by writing to the master reset and identity register (03h). such a write transfers the internally accumulated error count to the registers within 1s and simultaneously resets the internal counters to begin a new cycle of error accumulation. after the 1s period has elapsed, the rei error count registers may be read.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 70 address 10h: rsop control bit type function default bit 7 r/w bipword 0 bit 6 r/w dds 0 bit 5 w foof x bit 4 r/w algo2 0 bit 3 r/w bipee 0 bit 2 r/w lose 0 bit 1 r/w lofe 0 bit 0 r/w oofe 0 oofe: the oof interrupt enable is an interrupt mask for out of frame. when oofe is a logic one, a section interrupt is generated when oof is declared or removed. lofe: the lof interrupt enable is an interrupt mask for loss of frame. when lofe is a logic one, a section interrupt is generated when lof is declared or removed. lose: the los interrupt enable is an interrupt mask for loss of signal. when lose is a logic one, a section interrupt is generated when los is declared or removed. bipee: the section bip interrupt enable is an interrupt mask for section bip (b1) error events. when bipe is a logic one, a section interrupt is generated when a section bip error is detected. algo2: the algo2 bit position selects the framing algorithm used to confirm and maintain the frame alignment. when a logic one is written to the algo2 bit position, the framer is enabled to use the second of the framing algorithms where only the first a1 framing byte and the first 4 bits of the first a2 framing
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 71 byte (12 bits total) are examined. this algorithm examines only 12 bits of the framing pattern regardless of the sts mode; all other framing bits are ignored. when a logic zero is written to the algo2 bit position, the framer is enabled to use the first of the framing algorithms where all the a1 framing bytes and all the a2 framing bytes are examined. this algorithm examines all 16 bits of the framing pattern in sts-1 mode, and all 48 bits of the framing pattern in sts-3 mode. foof: when a logic one is written to the force out-of-frame (foof) bit location, the stxc is forced out-of-frame at the next frame boundary, regardless of the framing byte values. the out-of-frame event results in the assertion of the oof output and the oofv register bit. when operating in a byte serial mode, the oof output instructs an upstream framing pattern detector to attempt to find a new byte alignment. when operating in a bit serial mode, the reframe procedure is performed internally. the foof bit is a write only bit; an rsop control register read may yield a logic one or a logic zero in this bit position. dds: the disable descrambling (dds) bit controls the descrambling of the receive stream. when a logic one is written to the dds bit position, the descrambler is disabled. when a logic zero is written to the dds bit position, the descrambler is enabled. bipword: the bipword bit position enables the reporting and accumulating of section bip word errors. when a logic one is written to the bipword bit position, one or more errors in the bip-8 byte result in a single error indicated per frame on the b1e output and a single error accumulated in the b1 error counter. when a logic zero is written to the bipword bit position, all errors in the b1 byte are indicated per frame on the b1e output and are accumulated in the b1 error counter.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 72 address 11h: rsop interrupt status bit type function default bit 7 unused x bit 6 r bipei x bit 5 r losi x bit 4 r lofi x bit 3 r oofi x bit 2 r losv x bit 1 r lofv x bit 0 r oofv x oofv: the oofv bit is set high when out of frame is declared. oof is declared (oofv is high) while the stxc is unable to find a valid framing pattern (a1, a2) in the incoming stream. oof is removed when a valid framing pattern is detected. this alarm indication is also available on output oof. lofv: the lofv bit is set high when loss of frame is declared. lof is declared (lofv is high) when an out of frame state persists for 3 ms. lof is removed when an in frame state persists for 3 ms. this alarm indication is also available on output lof. losv: the losv bit is set high when loss of signal is declared. los is declared (losv is high) when 20 2.5 s of consecutive all zeros patterns is detected in the incoming stream. los is removed when two valid framing words (a1, a2) are detected, and during the intervening time (125 s), no violating period of all zeros patterns is observed. this alarm indication is also available on output los. oofi: the oofi bit is set high when out of frame is declared or removed. this bit is cleared when the rsop interrupt status register is read.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 73 lofi: the lofi bit is set high when loss of frame is declared or removed. this bit is cleared when the rsop interrupt status register is read. losi: the losi bit is set high when loss of signal is declared or removed. this bit is cleared when the rsop interrupt status register is read. bipei: the bipei bit is set high when a section bip error is detected. this bit is cleared when the rsop interrupt status register is read.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 74 address 12h: b1 error count #1 bit type function default bit 7 r be[7] x bit 6 r be[6] x bit 5 r be[5] x bit 4 r be[4] x bit 3 r be[3] x bit 2 r be[2] x bit 1 r be[1] x bit 0 r be[0] x address 13h: b1 error count #2 bit type function default bit 7 r be[15] x bit 6 r be[14] x bit 5 r be[13] x bit 4 r be[12] x bit 3 r be[11] x bit 2 r be[10] x bit 1 r be[9] x bit 0 r be[8] x be[15:0]: bits be[15] through be[0] represent the number of section bit-interleaved parity errors that have been detected since the last accumulation interval. the error counters are polled by writing to any of the b1 error count register addresses (12h, or 13h), or by writing to the master reset and identity register (03h). such a write transfers the internally accumulated error count to the registers within 1s and simultaneously resets the internal counters to begin a new cycle of error accumulation. after the 1s period has elapsed, the b1 error count registers may be read.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 75 address 14h: output port bit type function default bit 7 unused x bit 6 unused x bit 5 r/w scpo[5] 1 bit 4 r/w scpo[4] 1 bit 3 r/w scpo[3] 0 bit 2 r/w scpo[2] 0 bit 1 r/w scpo[1] 1 bit 0 r/w scpo[0] 0 scpo[4:0]: the values written to the scpo[4:0] bit in the output port register directly correspond to the states set on the scpo[4:0] output pins. this provides a generic port useful for controlling up to 5 signals. scpo[5]: the value written to the scpo[5] bit in the output port register directly corresponds to the state set on the scpo[5] output pin when either the enh bit or the rdpen bit in the mode select register is logic 0. this register bit is reserved when both the enh bit and the rdpen bit in the mode select register are logic 1.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 76 address 15h: input port interrupt enable bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w scpie[3] 0 bit 2 r/w scpie[2] 0 bit 1 r/w scpie[1] 0 bit 0 r/w scpie[0] 0 scpie[1:0] the scpie[1:0] bits are interrupt enables. when a logic one is written to these locations, the occurrence of an event on the corresponding scpi[1:0] input activates the interrupt (intb). the interrupt is cleared by reading the configuration input port status/value register. when a logic zero is written to these locations, the occurrence of an event on the corresponding scpi[1:0] input is inhibited from activating the interrupt. scpie[3:2] the scpie[3] bits are interrupt enables. when a logic one is written to these locations, the occurrence of an event on the scpi[3:2] input activates the interrupt (intb) when the enh bit in the mode select register is logic 0. the interrupt is cleared by reading the configuration input port status/value register. when a logic zero is written to these locations, the occurrence of an event on the corresponding scpi[3:2] inputs are inhibited from activating the interrupt. these register bits are reserved when the enh bit in the mode select register are logic 1.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 77 address 16h: mode select bit type function default bit 7 r/w oddpg 0 bit 6 r/w oddpc 0 bit 5 r/w incpl 0 bit 4 r/w incfp 0 bit 3 r/w c1en 0 bit 2 r/w rdpen 0 bit 1 r/w tsoutdis 0 bit 0 r/w enh 0 enh: the enh bit enables an enhanced stxc feature set. when enh is a logic 0, the enhanced feature set is disabled, and this version of the stxc is backwards compatible with previous versions. when enh is a logic 1, the enhanced feature set is enabled. the major features of this enhanced feature set include signal fail and signal degrade alarm threshold detection, and optional parity on the receive and transmit busses. note that certain register addresses are relocated when the enhanced feature set is enabled, and that the stxc register memory map and certain bit positions are not backwards compatible with earlier versions of the device. tsoutdis: the tsoutdis bit disables the transmit serial outgoing stream, tsout. when tsoutdis is 0 tsout contains the scrambled outgoing stream in bit serial format when serial sts-1 mode is selected. when tstoutdis is 1, or when sts-1 mode is not selected, tsout outputs logic 0. when enh is logic 0, tsoutdis is reserved. rdpen: the rdpen input configures the multifunction output scpo[5]/rdp, and enables parity generation on the receive bus. when rdpen is logic 1, scpo[5]/rdp reports the generated receive parity bit. when rdpen is a logic 0, or when enh is logic 0, the multifunction output scpo[5]/rdp is part of the generic control port.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 78 c1en: the c1en bit configures the multifunction input scpi[2]/tpl, as well as configures the frame pulse boundaries reported by tifp/tc1j1v1. when c1en is logic 0, or when enh is logic 0, the input scpi[2]/tpl is sampled as scpi[2]. also, tifp pulses high at the first spe byte following the z0 byte(s) to mark frame boundaries. when c1en is logic 1, scpi[2]/tpl sampled as tpl. also, scpi[2]/tpl is set low while tc1j1v1 pulses high at the j0 byte to mark farme boundaries. incfp: the incfp bit determines whether the frame pulse signal is included in the receive and transmit parity calculations. when incfp is logic 1, and when enh is logic 1, rofp is included in the receive parity generation when rdpen is logic 1, and tifp/tc1j1v1 is included in the trasmit parity calculation. when incfp is logic 0, rofp and tifp/tc1j1v1 are excluded from parity calculations. when enh is logic 0, incfp is reserved, and there are no parity calculations. incpl: the incpl bit determines whether the active payload signal is included in the trasmit parity calculation. when incpl is a logic 1, and c1en is logic 1, scpi[2]/tpl is included in the calculation. when incpl is a logic 0, or when c1en is logic 0, scpi[2]/tpl is excluded from the calculation. when enh is logic 0, incpl is reserved, and there are no parity calculations. oddpc: the oddpc bit controls the parity expected on the transmit bus. when oddpc is a logic 1, the bus parity including the tdp signal is odd. when oddpc is a logic 0, the bus parity including the tdp signal is even. oddpg: when parity generation is enabled, oddpg controls the parity expected on the receive bus. when oddpg is a logic 1, the bus parity including the rdp signal is odd. when oddpg is a logic 0, the bus parity including the rdp signal is even.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 79 address 17h: ring control bit type function default bit 7 r/w ringen 0 bit 6 r insrdi x bit 5 r insais x bit 4 r/w autorei 0 bit 3 r/w autordi 0 bit 2 r/w autorais 0 bit 1 r/w srdi 0 bit 0 r/w sais 0 sais: the sais bit controls the value of the sendais bit position in the receive ring control port stream. the sais bit is used to cause a mate stxc to send the line ais maintenance signal under software control. srdi: the srdi bit controls the value of the sendrdi bit position in the receive ring control port stream. the sendrdi bit value is determined by the logical or of this register bit, along with the loss of signal, loss of frame, and line ais alarm states when the enh bit in the mode select register is a logic 0. when the enh bit is a logic 1, the sendrdi bit value is determined by the logical or of this register bit along with the rdi insertion events programmed in he rdi control register. the srdi bit is used to cause a mate stxc to send the line rdi maintenance signal under software control. autorais: the autorais bit enables the automatic insertion of line ais in the receive direction. when autoais is logic one and the enh bit in the mode select register is logic zero, line ais is automatically inserted in rout[7:0] when los or lof is declared. ais is also conditionally inserted based on the contents of the section trace ais insertion register. when autoais is logic zero, automatic ais insertion is disabled. when enh is logic one, the autoais bit is reserved, and line ais is conditionally inserted in rout[7:0] based on the contents of the ais control register. note that the insertion of line ais is also controlled by the rlais input.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 80 autordi: the autordi bit enables the automatic insertion of line rdi in the transmit direction. when autordi is logic one and the enh bit in the mode select register is logic zero, line rdi is automatically inserted in the transmit stream when los, lof, or line ais is declared and when the ring control ports are disabled. when autordi is logic zero, automatic rdi insertion is disabled. when enh is logic one, the autordi bit is reserved, and line rdi is conditionally inserted in the transmit stream based on the contents of the rdi control register when the ring control ports are disabled. line rdi is automatically inserted in the transmit stream when the sendrdi bit position in the transmit ring control port is a logic 1 and when the ring control ports are enabled. note that the insertion of line rdi is also controlled by the trdi input (when the ring control ports are disabled) and the rdi bit in the tlop control register. autorei: the autorei bit enables the automatic insertion of line rei events in the transmit direction. when autorei is a logic one, receive b2 errors detected by the stxc (when the ring control ports are disabled), or from the transmit ring control port, (when the ring control ports are enabled) are automatically inserted in the z2 byte of the transmit stream. when autorei is a logic zero, line rei events are not automatically inserted in the transmit stream. a z2 byte inserted upstream of the stxc (using the tdis input) or inserted from the transmit transport overhead port (using the ttohen input) take precedence over the automatic insertion of rei events. insais: the insais bit reports the value of the sendais bit position in the transmit ring control port. when the ring control ports are enabled, a logic one in this bit position indicates that the stxc is inserting the line ais maintenance signal. insrdi: the insrdi bit reports the value of the sendrdi bit position in the transmit ring control port. when the ring control ports are enabled, a logic one in this bit position indicates that the stxc is inserting the line rdi maintenance signal.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 81 ringen: the ringen bit controls the operation of the transmit ring control port when the ring control ports are enabled by the rcp bit in the master control/enable register. when ringen is a logic one, the automatic insertion of line rdi, line ais, and line rei is controlled by bit positions in the transmit ring control port input stream. when ringen is a logic zero, the insertion of line rdi is done automatically based on alarms detected by the receive portion of the stxc. also, line rei is inserted based on b2 errors detected by the receive portion of the stxc.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 82 register 18h: tsop control bit type function default bit 7 unused x bit 6 r/w ds 0 bit 5 r/w ubt 0 bit 4 r/w dc1 0 bit 3 r/w duc 0 bit 2 r/w ddl 0 bit 1 r/w dow 0 bit 0 r/w lais 0 lais: the lais bit controls the insertion of line alarm indication signal (ais). when lais is set high, the tsop inserts line ais into the transmit stream. activation or deactivation of line ais insertion is synchronized to frame boundaries. dow: the dow bit controls the overwriting of the local orderwire byte (e1). when dow is logic one, the value sampled on tin[7:0] during the e1 byte position is passed through the transmit section overhead processor unaltered, as though the tdis input had been sampled high during the e1 byte position in the incoming frame. the upstream insertion of the express orderwire is thus accomplished without the use of the tdis input. note that only the e1 byte position is passed unaltered, the remaining 2 (sts-3/stm-1) byte positions are overwritten with all zeros. this overwriting may be defeated by using the tdis input, or by using the ubt bit in this register. when dow is logic zero, the section order wire source is nominally the tsow input (while tdis and ttohen are both low). ddl: the ddl bit controls the overwriting of the section data communications channel (d1 - d3). when ddl is logic one, the values sampled on tin[7:0] during the d1 - d3 byte positions are passed through the transmit section overhead processor unaltered, as though the tdis input had been sampled high during the d1 - d3 byte positions in the incoming frame. the upstream
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 83 insertion of the section dcc is thus accomplished without the use of the tdis input. note that only the d1 -d3 byte positions are passed unaltered, the remaining 6 (sts-3/stm-1) undefined byte positions are overwritten with all zeros. this overwriting may only be defeated by using the tdis input, or by using the ubt bit in this register. when ddl is logic zero, the section dcc source is nominally the tsd input (while tdis and ttohen are both low). duc: the duc bit controls the overwriting of the section user channel byte (f1). when duc is logic one, the value sampled on tin[7:0] during the f1 byte position is passed through the transmit section overhead processor unaltered, as though the tdis input had been sampled high during the f1 byte position in the incoming frame. the upstream insertion of the user channel is thus accomplished without the use of the tdis input. note that only the f1 byte position is passed unaltered, the remaining 2 (sts-3/stm-1) undefined byte positions are overwritten with all zeros. this overwriting may only be defeated by using the tdis input, or by using the ubt bit in this register. when duc is logic zero, the section user channel source is nominally the tsuc input (while tdis and ttohen are both low). dc1: the dc1 bit controls the overwriting of the identity bytes (j0/z0). when dc1 is logic one, the values sampled on tin[7:0] during the j0/z0 byte positions are passed through the transmit section overhead processor unaltered, as though the tdis input had been sampled high during the j0/z0 byte positions in the incoming frame. the upstream insertion of the identity is thus accomplished without the use of the tdis input. note that all 1 (sts-1) or 3 (sts-3/stm-1) identification bytes are passed through unaltered. when dc1 is logic zero, the identity bytes are programmed as specified in the north american references: sts-1 #1 j0 = 01h, sts-1 #2 z0 = 02h, and sts-1 #3 z0 = 03h. the dc1 bit has no effect on sts-1 #1 when the sten bit of the master configuration register is a logic one. ubt: the ubt bit controls the overwriting of the unused byte positions in the transmit sts-3/stm-1 stream. the unused bytes are contained in the b1, e1, f1, d1, d2, and d3 byte positions of sts-1 #2 and sts-1 #3. when ubt is logic zero, the unused byte positions are overwritten with all zeros. when ubt is logic one, the values sampled on tin[7:0] during the unused byte positions are passed through the transmit section overhead processor unaltered, as though the tdis input had been sampled high during the unused byte positions in the incoming frame.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 84 ds: the disable scrambling (ds) bit controls the scrambling of the transmit stream. when a logic one is written to the ds bit position, the scrambler is disabled. when a logic zero is written to the ds bit position, the scrambler is enabled.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 85 register 19h: tsop diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w dlos 0 bit 1 r/w dbip8 0 bit 0 r/w dfp 0 dfp: the dfp bit controls the insertion of a single bit error continuously in the most significant bit (bit 1) of the a1 section overhead framing byte. if dfp is set high the a1 bytes are set to 76h instead of f6h. dbip8: the dbip8 bit controls the insertion of bit errors continuously in the b1 section overhead byte. when dbip8 is set high the b1 byte value is inverted. dlos: the dlos bit controls the insertion of all zeros in the transmit outgoing stream. when dlos is set high the tout[7:0] data bus is forced to 00h and the transmit serial stream (tsout or txd+/-) is forced low.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 86 register 1ah: transmit z1 bit type function default bit 7 r/w z1[7] 0 bit 6 r/w z1[6] 0 bit 5 r/w z1[5] 0 bit 4 r/w z1[4] 0 bit 3 r/w z1[3] 0 bit 2 r/w z1[2] 0 bit 1 r/w z1[1] 0 bit 0 r/w z1[0] 0 in sts-3/stm-1 operation, the value 00h is inserted into the the z1 byte for sts-1#2 and sts-1#3, irrespective of the value of register 1ah. the ttohen and tdis inputs take precedence over this insertion value. z1[7:0]: the value written to these bit positions is inserted in the first z1 byte position of the transmit stream. the z1 byte is used to carry synchronization status messages between line terminating network elements. z1[7] is the most significant bit corresponding to bit 1, the first bit transmitted. z1[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. the ttohen and tdis inputs take precedence over the contents of this register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 87 register 1bh: receive z1 (enh=0) bit type function default bit 7 r z1[7] x bit 6 r z1[6] x bit 5 r z1[5] x bit 4 r z1[4] x bit 3 r z1[3] x bit 2 r z1[2] x bit 1 r z1[1] x bit 0 r z1[0] x z1[7:0]: the first z1 byte contained in the receive stream is extracted into this register when the enh bit in the mode select register is a logic 0. the z1 byte is used to carry synchronization status messages between line terminating network elements. z1[7] is the most significant bit corresponding to bit 1, the first bit received. z1[0] is the least significant bit, corresponding to bit 8, the last bit received. an interrupt may be generated when a byte value is received that differs from the value extracted in the previous frame (using the z1e bit in the master control/enable register).
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 88 register 1bh: transmit z0 (enh=1) bit type function default bit 7 r/w z0[7] 1 bit 6 r/w z0[6] 1 bit 5 r/w z0[5] 0 bit 4 r/w z0[4] 0 bit 3 r/w z0[3] 1 bit 2 r/w z0[2] 1 bit 1 r/w z0[1] 0 bit 0 r/w z0[0] 0 z0[7:0]: z0[7:0] contains the value inserted in z0 bytes for sts-1 #2 and #3 in the transmit sts-3/stm-1 stream when the enh bit in the mode select register and the z0ins bit in the master control/enable register are both logic 1. z0[7] is the most significant bit corresponding to bit 1, the first bit transmitted. z0[0] is the least significant bit, corresponding to bit 8, the last bit transmitted.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 89 address 1dh: receive k1 (enh=0) bit type function default bit 7 r k1[7] x bit 6 r k1[6] x bit 5 r k1[5] x bit 4 r k1[4] x bit 3 r k1[3] x bit 2 r k1[2] x bit 1 r k1[1] x bit 0 r k1[0] x k1[7:0]: the k1[7:0] bits contain the current k1 code value when the enh bit in the mode select register is a logic 0. the contents of this register are updated when a new k1 code value (different from the current k1 code value) has been received for three consecutive frames. an interrupt may be generated when a new code value is received (using the coapse bit in the master control/enable register). k1[7] is the most significant bit corresponding to bit 1, the first bit received. k1[0] is the least significant bit, corresponding to bit 8, the last bit received.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 90 address 1dh: ais control (enh=1) bit type function default bit 7 r/w sdins 0 bit 6 r/w sfins 0 bit 5 r/w lofins 1 bit 4 r/w losins 1 bit 3 r/w rtimins 0 bit 2 r/w rtiuins 0 bit 1 unused x bit 0 r/w dccais 0 dccais: the dccais bit enables the insertion of all ones in the section dcc (rsd) and the line dcc (rld) when loss of frame (lof) or los is declared. when dccais is a logic 1, all ones is inserted in rsd and rld when lof or los is declared. rtiuins: the rtiuins bit enables the insertion of line ais in the receive direction upon the declaration of section trace unstable when the enh bit in the mode select register is a logic 1. if rtiuins is a logic 1, line ais is inserted into rout[7:0] when the current received section trace identifier message has not matched the previous message for eight consecutive messages. line ais is terminated when the current message becomes the accepted message. rtimins: the rtimins bit enables the insertion of line ais in the receive direction upon the declaration of section trace mismatch when the enh bit in the mode select register is a logic 1. if rtimins is a logic 1, line ais is inserted into rout[7:0] when the accepted identifier message differs from the expected message. line ais is terminated when the accepted message matches the expected message. losins: the losins bit enables the insertion of line ais in the receive direction upon the declaration of loss of signal (los) when the enh bit in the mode select
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 91 register is a logic 1. if losins is a logic 1, line ais is inserted into rout[7:0] when los is declared. line ais is terminated when los is removed. lofins: the lofins bit enables the insertion of line ais in the receive direction upon the declaration of loss of frame (lof) when the enh bit in the mode select register is a logic 1. if losins is a logic 1, line ais is inserted into rout[7:0] when los is declared. line ais is terminated when los is removed. sfins: the sfins bit enables the insertion of line ais in the receive direction upon the declaration of signal fail (sf) when the enh bit in the mode select register is a logic 1. if sfins is a logic 1, line ais is inserted into rout[7:0] when sf is declared. line ais is terminated when sf is removed. sdins: the sdins bit enables the insertion of line ais in the receive direction upon the declaration of signal degrade (sd) when the enh bit in the mode select register is a logic 1. if sdins is a logic 1, line ais is inserted into rout[7:0] when sd is declared. line ais is terminated when sd is removed.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 92 address 1eh: receive k2 (enh=0) bit type function default bit 7 r k2[7] x bit 6 r k2[6] x bit 5 r k2[5] x bit 4 r k2[4] x bit 3 r k2[3] x bit 2 r k2[2] x bit 1 r k2[1] x bit 0 r k2[0] x k2[7:0]: the k2[7:0] bits contain the current k2 code value when the enh bit in the mode select register is a logic 0. the contents of this register are updated when a new k2 code value (different from the current k2 code value) has been received for three consecutive frames. an interrupt may be generated when a new code value is received (using the coapse bit in the master control/enable register). k2[7] is the most significant bit corresponding to bit 1, the first bit received. k2[0] is the least significant bit, corresponding to bit 8, the last bit received.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 93 address 1eh: rdi control (enh=1) bit type function default bit 7 r/w sdins 0 bit 6 r/w sfins 0 bit 5 r/w lofins 1 bit 4 r/w losins 1 bit 3 r/w rtimins 0 bit 2 r/w rtiuins 0 bit 1 r/w aisins 1 bit 0 unused x aisins: the aisins bit enables the insertion of line rdi in the transmit stream or the receive ring control port upon the declaration of line ais. when aisins is a logic 1, the detection of line ais results in the insertion of line rdi in the transmit stream (when the ring control ports are disabled), or in the insertion of a logic 1 in the sendrdi bit position in the receive ring control port (when the ring control ports are enabled). rtiuins: the rtiuins bit enables the insertion of line rdi in the transmit stream or the receive ring control port upon the declaration of section trace unstable. when rtiuins is a logic 1, the detection of section trace unstable results in the insertion of line rdi in the transmit stream (when the ring control ports are disabled), or in the insertion of a logic 1 in the sendrdi bit position in the receive ring control port (when the ring control ports are enabled). rtimins: the rtimins bit enables the insertion of line rdi in the transmit stream or the receive ring control port upon the declaration of section trace mismatch. when rtimins is a logic 1, the detection of section trace mismatch results in the insertion of line rdi in the transmit stream (when the ring control ports are disabled), or in the insertion of a logic 1 in the sendrdi bit position in the receive ring control port (when the ring control ports are enabled).
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 94 losins: the aisins bit enables the insertion of line rdi in the transmit stream or the receive ring control port upon the declaration of loss of signal. when losins is a logic 1, the detection of los results in the insertion of line rdi in the transmit stream (when the ring control ports are disabled), or in the insertion of a logic 1 in the sendrdi bit position in the receive ring control port (when the ring control ports are enabled). lofins: the lofins bit enables the insertion of line rdi in the transmit stream or the receive ring control port upon the declaration of loss of frame. when lofins is a logic 1, the detection of lof results in the insertion of line rdi in the transmit stream (when the ring control ports are disabled), or in the insertion of a logic 1 in the sendrdi bit position in the receive ring control port (when the ring control ports are enabled). sfins: the sfins bit enables the insertion of line rdi in the transmit stream or the receive ring control port upon the declaration of signal failure. when sfins is a logic 1, the detection of sf results in the insertion of line rdi in the transmit stream (when the ring control ports are disabled), or in the insertion of a logic 1 in the sendrdi bit position in the receive ring control port (when the ring control ports are enabled). sdins: the sdins bit enables the insertion of line rdi in the transmit stream or the receive ring control port upon the declaration of signal degrade. when sdins is a logic 1, the detection of sd results in the insertion of line rdi in the transmit stream (when the ring control ports are disabled), or in the insertion of a logic 1 in the sendrdi bit position in the receive ring control port (when the ring control ports are enabled).
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 95 address 1fh: configuration input port status/value bit type function default bit 7 r scpiv[3] x bit 6 r scpiv[2] x bit 5 r scpiv[1] x bit 4 r scpiv[0] x bit 3 r scpii[3] x bit 2 r scpii[2] x bit 1 r scpii[1] x bit 0 r scpii[0] x scpii[2:0]: the scpii[2:0] bits are interrupt indications. a logic one in any bit location indicates that an event has occurred on the corresponding scpi[2:0] input. more specifically, a logic one in the scpii[2] bit location indicates that the signal on scpi[2] input has transitioned from logic zero to logic one (i.e. upon detection of a rising edge); a logic one in any of the scpii[1:0] bit locations indicates that the signal on the corresponding scpi[1:0] input has transitioned either from logic zero to logic one or from logic one to logic zero (i.e. upon a change of state). the scpii[2:0] bits are cleared by reading this register. these register bits function independently from the configuration input port enable register bits; the scpii[2:0] bits will indicate events occurring on the scpi[2:0] inputs regardless of whether or not these events are enabled to generate an interrupt. the scpii[2] bit is reserved when the enh bit in the mode select register are logic 1. scpii[3]: the scpii[3] bit is an interrupt indication. a logic one indicates that an event has occurred on the scpi[3] input. more specifically, a logic one in the scpii[3] bit location indicates that the signal on scpi[3] input has transitioned from logic zero to logic one (i.e. upon detection of a rising edge). the scpii[3] bit is cleared by reading this register. this register bit functions independently from the configuration input port enable register bits; the scpii[3] bit indicates events occurring on the scpi[3] input regardless of whether or not this event is enabled to generate an interrupt. this register bit is reserved when the enh bit in the mode select register are logic 1.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 96 scpiv[3:0]: the scpiv[3:0] bits are real-time input port state indications. a logic one in any bit location indicates that the signal on the corresponding scpi[3:0] input is a logic one. a logic zero in any bit location indicates that the signal on the corresponding scpi[3:0] input is a logic zero. the state of the scpi[3:0] inputs are latched and held during a microprocessor read of this register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 97 register 20h: section trace control (enh=0) bit type function default bit 7 unused x bit 6 r/w rramacc 0 bit 5 r/w rtiuie 0 bit 4 r/w rtimie 0 bit 3 r/w per5 0 bit 2 r/w tnull 1 bit 1 r/w nosync 0 bit 0 r/w len16 0 len16: the section trace message length bit (len16) selects the length of the section trace message to be 16 bytes or 64 bytes. nosync: the section trace message synchronization disable bit (nosync) disables the writing of the section trace message into the trace buffer to be synchronized to the content of the message. when len16 is set high and nosync is set low, the receive section trace message byte with its most significant bit set will be written to the first location in the buffer. when len16 is set low, and nosync is also set low, the byte after the carriage return/linefeed (cr/lf) sequence will be written to the first location in the buffer. when nosync is set high, synchronization is disabled, and the section trace message buffer behaves as a circular buffer. tnull: the transmit null bit (tnull) controls the insertion of an all-zero section trace identifier message in the transmit stream. when tnull is set high, the contents of the transmit buffer are ignored and all-zeros bytes are provided to the tpop block. when tnull is set low the contents of the transmit section trace buffer is sent to tpop. tnull should be set high before changing the contents of the trace buffer to avoid sending partial messages.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 98 per5: the receive trace identifier persistence bit (per5) control the number of times a section trace identifier message must be received unchanged before being accepted. when per5 is set high, a message is accepted when it is received unchanged five times consecutively. when per5 is set low, the message is accepted after three identical repetitions. rtimie: the receive section trace identifier message mismatch interrupt enable bit (rtimie) controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state from match to mismatch and vice versa. when rtimie is set high, changes in match state activates the interrupt (intb) output. when rtimie is set low, section trace identifier message state changes will not affect intb. rtiuie: the receive section trace identifier message unstable interrupt enable bit (rtiuie) controls the activation of the interrupt output when the receive identifier message state changes from stable to unstable and vice versa. the unstable state is entered when the current identifier message differs from the previous message for eightconsecutive messages. the stable state is entered when the same identifier message is received for three or five consecutive messages as controlled by the per5 bit. when rtiuie is set high, changes in the received section trace identifier message stable/unstable state will activate the interrupt (intb) output. when rtiuie is set low, section trace identifier state changes will not affect intb. rramacc: the receive ram access control bit (rramacc) directs read and writes access to between the receive and transmit portion of the section trace buffers. when rramacc is set high, subsequent microprocessor read and write accesses are directed to the receive side trace buffers. when rramacc is set low, microprocessor accesses are directed to the transmit side trace buffer.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 99 register 20h: rase interrupt enable (enh=1) bit type function default bit 7 r/w psbfe 0 bit 6 r/w coapse 0 bit 5 r/w z1e 0 bit 4 r/w sfbere 0 bit 3 r/w sdbere 0 bit 2 r/w unused x bit 1 r/w unused x bit 0 r/w unused x sdbere: the sdbere bit is the interrupt enable for the signal degrade threshold alarm. when sdbere is a logic one, an interrupt is generated when the sd alarm is declared or removed. sfbere: the sfbere bit is the interrupt enable for the signal fail threshold alarm. when sfbere is a logic one, an interrupt is generated when the sf alarm is declared or removed. z1e: the z1 interrupt enable is an interrupt mask for changes in the received synchronization status. when z1e is a logic one, an interrupt is generated when a new synchronization status message is extracted into the receive z1 register. coapse: the coaps interrupt enable is an interrupt mask for changes in the received aps code. when coapse is a logic one, an interrupt is generated when a new k1/k2 code value is extracted into the receive k1 and receive k2 registers.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 100 psbfe: the psbf interrupt enable is an interrupt mask for protection switch byte failure alarms. when psbfe is a logic one, an interrupt is generated when psbf is declared or removed.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 101 register 21h: section trace status (enh=0): bit type function default bit 7 r busy 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r rtiui x bit 2 r rtiuv x bit 1 r rtimi x bit 0 r rtimv x this register reports the section trace status. rtimv: the receive section trace identifier message mismatch status bit (rtimv) reports the match/mismatch status of the identifier message framer. rtimv is set high when the accepted identifier message differs from the expected message written by the microprocessor. rtimv is set low when the accepted message matches the expected message. rtimi: the receive section trace identifier mismatch interrupt status bit (rtimi) is set high when match/mismatch status of the trace identifier framer changes state. this bit (and the interrupt) are cleared when this register is read. rtiuv: the receive section trace identifier message unstable status bit (rtiuv) reports the stable/unstable status of the identifier message framer. rtiuv is set high when the current received section trace identifier message has not matched the previous message for eight consecutive messages. rtiuv is set low when the current message becomes the accepted message. rtiui: the receive section trace identifier message unstable interrupt status bit (rtiui) is set high when stable/unstable status of the trace identifier framer
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 102 changes state. this bit (and the interrupt) are cleared when this register is read. busy: the busy bit reports whether a previously initiated indirect read or write to a message buffer has been completed. busy is set high upon writing to the section trace indirect address register, and stays high until the initiated access has completed. at which point, busy is set low. this register should be polled to determine when new data is available in the section trace indirect data register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 103 register 21h: rase interrupt status (enh=1) bit type function default bit 7 r psbfi x bit 6 r coapsi x bit 5 r z1i x bit 4 r sfberi x bit 3 r sdberi x bit 2 r sfberv x bit 1 r sdberv x bit 0 r psbfv x psbfv: the psbfv bit indicates the protection switching byte failure alarm state. the alarm is declared (psbfv is set high) when twelve successive frames, where no three consecutive frames contain identical k1 bytes, have been received. the alarm is removed (psbfv is set low) when three consecutive frames containing identical k1 bytes have been received. this bit position is reserved when the enh bit in the mode select register is a logic 1. sdberv: the sdberv bit indicates the signal degrade threshold crossing alarm state. the alarm is declared (sdberv is set high) when the bit error rate exceeds the threshold programmed in the sd declaring threshold registers. the alarm is removed (sdberv is set low) when the bit error rate is below the threshold programmed in the sd clearing threshold registers. sfberv: the sfberv bit indicates the signal failure threshold crossing alarm state. the alarm is declared (sfberv is set high) when the bit error rate exceeds the threshold programmed in the sf declaring threshold registers. the alarm is removed (sfberv is set low) when the bit error rate is below the threshold programmed in the sf clearing threshold registers.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 104 sdberi: the sdberi bit is set high when the signal degrade threshold crossing alarm is declared or removed. this bit is cleared when the rase interrupt status register is read. sfberi: the sfberi bit is set high when the signal failure threshold crossing alarm is declared or removed. this bit is cleared when the rase interrupt status register is read. z1i: the z1i bit is set high when a new synchronization status message has been extracted into the receive z1 register. this bit is cleared when the rase interrupt status register is read. coapsi: the coapsi bit is set high when a new aps code value has been extracted into the receive k1 and receive k2 registers. this bit is cleared when the rase interrupt status register is read. psbfi: the psbfi bit is set high when the protection switching byte failure alarm is declared or removed. this bit is cleared when the rase interrupt status register is read.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 105 register 22h: section trace indirect address register (enh=0): bit type function default bit 7 r/w rwb 0 bit 6 r/w a[6] 0 bit 5 r/w a[5] 0 bit 4 r/w a[4] 0 bit 3 r/w a[3] 0 bit 2 r/w a[2] 0 bit 1 r/w a[1] 0 bit 0 r/w a[0] 0 this register supplies the address used to index into section trace identifier buffers. a[6:0]: the indirect read address bits (a[6:0]) indexes into the section trace identifier buffers. when rramacc is set high, addresses 0 to 63 reference the receive capture page while addresses 64 to 127 reference the receive expected page. the receive capture page contains the identifier bytes extracted from the receive stream. the receive expected page contains the expected trace identifier message down-loaded from the microprocessor. when rramacc is set low, addresses 0 to 63 reference the transmit message buffer which contains the identifier message to be inserted into the j0 byte of the transmit stream. addresses 64 to 127 are unused and must not be accessed. rwb: the access control bit (rwb) selects between an indirect read or write access to the static page of the section trace message buffer. writing to this register initiates an external microprocessor access to the static page of the section trace message buffer. when rwb is set high, a read access is initiated. the data read can be found in the section trace indirect data register. when rwb is set low, a write access is initiated. the data in the section trace indirect data register will be written to the addressed location in the static page.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 106 register 22h: rase configuration/control register (enh=1): bit type function default bit 7 r/w z1_cap3 0 bit 6 r/w sfberten 0 bit 5 r/w sfsmode 0 bit 4 r/w sfcmode 0 bit 3 r/w sdberten 0 bit 2 r/w sdsmode 0 bit 1 r/w sdcmode 0 bit 0 r/w unused x sdcmode: the sdcmode alarm bit selects the sd berm window size to use for clearing the sd alarm. when sdcmode is a logic 0 the sd berm clears the sd alarm using the same window size used for declaration. when sdcmode is a logic 1 the sd berm clears the sd alarm using a window size that is 8 times longer than the alarm declaration window size. the declaration window size is determined by the sd berm accumulation period registers. sdsmode: the sdsmode bit selects the sd berm saturation mode. when sdsmode is a logic 0 the sd berm limits the number of b2 errors accumulated in one frame period to the sd saturation threshold register value. when sdsmode is a logic 1 the sd berm limits the number of b2 errors accumulated in one window subtotal accumulation period to the sd saturation threshold register value. note that the number of frames in a window subtotal accumulation period is determined by the sd accumulation period register value. sdberten: the sdberten bit selects automatic monitoring of line bit error rate threshold events by the signal degrade bit error rate monitor (sd berm). when sdberten is a logic one, the sd berm continuously monitors line bip errors over a period defined in the berm configuration registers. when sdberten is a logic zero, the sd berm bip accumulation logic is disabled, and the berm logic is reset to the declaration monitoring state.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 107 all sd berm accumulation period and threshold registers should be set up before sdberten is written. sfcmode: the sfcmode alarm bit selects the sf berm window size to use for clearing the sf alarm. when sfcmode is a logic 0 the sf berm clears the sf alarm using the same window size used for declaration. when sfcmode is a logic 1 the sf berm clears the sf alarm using a window size that is 8 times longer than the alarm declaration window size. the declaration window size is determined by the sf berm accumulation period registers. sfsmode: the sfsmode bit selects the sf berm saturation mode. when sfsmode is a logic 0 the sf berm limits the number of b2 errors accumulated in one frame period to the sf saturation threshold register value. when sfsmode is a logic 1 the sf berm limits the number of b2 errors accumulated in one window subtotal accumulation period to the sf saturation threshold register value. note that the number of frames in a window subtotal accumulation period is determined by the sf accumulation period register value. sfberten: the sfberten bit enables automatic monitoring of line bit error rate threshold events by the signal failure bit error rate monitor (sf berm). when sfberten is a logic one, the sf berm continuously monitors line bip errors over a period defined in the berm configuration registers. when sfberten is a logic zero, the sf berm bip accumulation logic is disabled, and the berm logic is reset to the declaration monitoring state. all sf berm accumulation period and threshold registers should be set up before sfberten is written. z1_cap3: the z1_cap3 bit enables the z1 capture algorithm. when z1_cap3 is a logic one, the z1 nibble must have the same value for three consecutive frames before writing the new value into the receive z1 register. when z1_cap3 is logic zero, the z1 nibble value is written directly into the receive z1 register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 108 register 23h: section trace indirect data register (enh=0) bit type function default bit 7 r/w d[7] 0 bit 6 r/w d[6] 0 bit 5 r/w d[5] 0 bit 4 r/w d[4] 0 bit 3 r/w d[3] 0 bit 2 r/w d[2] 0 bit 1 r/w d[1] 0 bit 0 r/w d[0] 0 this register contains the data read from the section trace message buffer after a read operation or the data to be written into the buffer before a write operation. d[7:0]: the indirect data bits (d[7:0]) reports the data read from a message buffer after an indirect read operation has completed. the data to be written to a buffer must be set up in this register before initiating an indirect write operation.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 109 register 23h: rase sf accumulation period (lsb, enh=1) bit type function default bit 7 r/w sfsap[7] 0 bit 6 r/w sfsap[6] 0 bit 5 r/w sfsap[5] 0 bit 4 r/w sfsap[4] 0 bit 3 r/w sfsap[3] 0 bit 2 r/w sfsap[2] 0 bit 1 r/w sfsap[1] 0 bit 0 r/w sfsap[0] 0 register 24h: rase sf accumulation period (enh=1) bit type function default bit 7 r/w sfsap[15] 0 bit 6 r/w sfsap[14] 0 bit 5 r/w sfsap[13] 0 bit 4 r/w sfsap[12] 0 bit 3 r/w sfsap[11] 0 bit 2 r/w sfsap[10] 0 bit 1 r/w sfsap[9] 0 bit 0 r/w sfsap[8] 0 register 25h: rase sf accumulation period (msb, enh=1) bit type function default bit 7 r/w sfsap[23] 0 bit 6 r/w sfsap[22] 0 bit 5 r/w sfsap[21] 0 bit 4 r/w sfsap[20] 0 bit 3 r/w sfsap[19] 0 bit 2 r/w sfsap[18] 0 bit 1 r/w sfsap[17] 0 bit 0 r/w sfsap[16] 0
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 110 sfsap[23:0]: the sfsap[23:0] bits represent the number of 8 khz frames used to accumulate the b2 error subtotal. the total evaluation window to declare the sf alarm is broken into 8 subtotals, so this register value represents 1/8 of the total sliding window size. refer to the operations section for recommended settings.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 111 register 26h: rase sf saturation threshold (lsb, enh=1) bit type function default bit 7 r/w sfsth[7] 0 bit 6 r/w sfsth[6] 0 bit 5 r/w sfsth[5] 0 bit 4 r/w sfsth[4] 0 bit 3 r/w sfsth[3] 0 bit 2 r/w sfsth[2] 0 bit 1 r/w sfsth[1] 0 bit 0 r/w sfsth[0] 0 register 27h: rase sf saturation threshold (msb, enh=1) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w sfsth[11] 0 bit 2 r/w sfsth[10] 0 bit 1 r/w sfsth[9] 0 bit 0 r/w sfsth[8] 0 sfsth[11:0]: the sfsth[11:0] value represents the allowable number of b2 errors that can be accumulated during an evaluation window before an sf threshold event is declared. setting this threshold to 0xfff disables the saturation functionality. refer to the operations section for the recommended settings.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 112 register 28h: section trace ais insertion (enh=0) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w rtiu_ais 0 bit 0 r/w rtim_ais 0 this register enables the insert of line ais into the rout[7:0] byte stream upon a section trace alarm condition. rtim_ais: the rtim_ais bit enables the insertion of line ais upon the declaration of a section trace mismatch. if rtim_ais is a logic one, line ais is inserted into rout[7:0] when the accepted identifier message differs from the expected message. line ais is terminated when the accepted message matches the expected message. rtiu_ais: the rtiu_ais bit enables the insertion of line ais upon the declaration of section trace unstable. if rtiu_ais is a logic one, line ais is inserted into rout[7:0] when the current received section trace identifier message has not matched the previous message for eight consecutive messages. line ais is terminated when the current message becomes the accepted message.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 113 register 28h: rase sf declaring threshold (lsb, enh=1) bit type function default bit 7 r/w sfdth[7] 0 bit 6 r/w sfdth[6] 0 bit 5 r/w sfdth[5] 0 bit 4 r/w sfdth[4] 0 bit 3 r/w sfdth[3] 0 bit 2 r/w sfdth[2] 0 bit 1 r/w sfdth[1] 0 bit 0 r/w sfdth[0] 0 register 29h: rase sf declaring threshold (msb, enh=1) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w sfdth[11] 0 bit 2 r/w sfdth[10] 0 bit 1 r/w sfdth[9] 0 bit 0 r/w sfdth[8] 0 sfdth[11:0]: the sfdth[11:0] value determines the threshold for the declaration of the sf alarm. the sf alarm is declared when the number of b2 errors accumulated during an evaluation window is greater than or equal to the sfdth[11:0] value. refer to the operations section for the recommended settings.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 114 register 2ah: rase sf clearing threshold (lsb, enh=1) bit type function default bit 7 r/w sfcth[7] 0 bit 6 r/w sfcth[6] 0 bit 5 r/w sfcth[5] 0 bit 4 r/w sfcth[4] 0 bit 3 r/w sfcth[3] 0 bit 2 r/w sfcth[2] 0 bit 1 r/w sfcth[1] 0 bit 0 r/w sfcth[0] 0 register 2bh: rase sf clearing threshold (msb, enh=1) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w sfcth[11] 0 bit 2 r/w sfcth[10] 0 bit 1 r/w sfcth[9] 0 bit 0 r/w sfcth[8] 0 sfcth[11:0]: the sfcth[11:0] value determines the threshold for the removal of the sf alarm. the sf alarm is removed when the number of b2 errors accumulated during an evaluation window is less than the sfcth[11:0] value. refer to the operations section for the recommended settings.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 115 register 2ch: rase sd accumulation period (lsb, enh=1) bit type function default bit 7 r/w sdsap[7] 0 bit 6 r/w sdsap[6] 0 bit 5 r/w sdsap[5] 0 bit 4 r/w sdsap[4] 0 bit 3 r/w sdsap[3] 0 bit 2 r/w sdsap[2] 0 bit 1 r/w sdsap[1] 0 bit 0 r/w sdsap[0] 0 register 2dh: rase sd accumulation period (enh=1) bit type function default bit 7 r/w sdsap[15] 0 bit 6 r/w sdsap[14] 0 bit 5 r/w sdsap[13] 0 bit 4 r/w sdsap[12] 0 bit 3 r/w sdsap[11] 0 bit 2 r/w sdsap[10] 0 bit 1 r/w sdsap[9] 0 bit 0 r/w sdsap[8] 0 register 2eh: rase sd accumulation period (msb, enh=1) bit type function default bit 7 r/w sdsap[23] 0 bit 6 r/w sdsap[22] 0 bit 5 r/w sdsap[21] 0 bit 4 r/w sdsap[20] 0 bit 3 r/w sdsap[19] 0 bit 2 r/w sdsap[18] 0 bit 1 r/w sdsap[17] 0 bit 0 r/w sdsap[16] 0
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 116 sdsap[23:0]: the sdsap[23:0] bits represent the number of 8 khz frames used to accumulate the b2 error subtotal. the total evaluation window to declare the sd alarm is broken into 8 subtotals, so this register value represents 1/8 of the total sliding window size. refer to the operations section for recommended settings.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 117 register 2fh: rase sd saturation threshold (lsb, enh=1) bit type function default bit 7 r/w sdsth[7] 0 bit 6 r/w sdsth[6] 0 bit 5 r/w sdsth[5] 0 bit 4 r/w sdsth[4] 0 bit 3 r/w sdsth[3] 0 bit 2 r/w sdsth[2] 0 bit 1 r/w sdsth[1] 0 bit 0 r/w sdsth[0] 0 register 30h: rase sd saturation threshold (msb, enh=1) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w sdsth[11] 0 bit 2 r/w sdsth[10] 0 bit 1 r/w sdsth[9] 0 bit 0 r/w sdsth[8] 0 sdsth[11:0]: the sdsth[11:0] value represents the allowable number of b2 errors that can be accumulated during an evaluation window before an sd threshold event is declared. setting this threshold to 0xfff disables the saturation functionality. refer to the operations section for the recommended settings.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 118 register 31h: rase sd declaring threshold (lsb, enh=1) bit type function default bit 7 r/w sddth[7] 0 bit 6 r/w sddth[6] 0 bit 5 r/w sddth[5] 0 bit 4 r/w sddth[4] 0 bit 3 r/w sddth[3] 0 bit 2 r/w sddth[2] 0 bit 1 r/w sddth[1] 0 bit 0 r/w sddth[0] 0 register 32h: rase sd declaring threshold (msb, enh=1) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w sddth[11] 0 bit 2 r/w sddth[10] 0 bit 1 r/w sddth[9] 0 bit 0 r/w sddth[8] 0 sddth[11:0]: the sddth[11:0] value determines the threshold for the declaration of the sd alarm. the sd alarm is declared when the number of b2 errors accumulated during an evaluation window is greater than or equal to the sddth[11:0] value. refer to the operations section for the recommended settings.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 119 register 33h: rase sd clearing threshold (lsb, enh=1) bit type function default bit 7 r/w sdcth[7] 0 bit 6 r/w sdcth[6] 0 bit 5 r/w sdcth[5] 0 bit 4 r/w sdcth[4] 0 bit 3 r/w sdcth[3] 0 bit 2 r/w sdcth[2] 0 bit 1 r/w sdcth[1] 0 bit 0 r/w sdcth[0] 0 register 34h: rase sd clearing threshold (msb, enh=1) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w sdcth[11] 0 bit 2 r/w sdcth[10] 0 bit 1 r/w sdcth[9] 0 bit 0 r/w sdcth[8] 0 sdcth[11:0]: the sdcth[11:0] value determines the threshold for the removal of the sd alarm. the sd alarm is removed when the number of b2 errors accumulated during an evaluation window is less than the sdcth[11:0] value. refer to the operations section for the recommended settings.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 120 address 35h: receive k1 (enh=1) bit type function default bit 7 r k1[7] x bit 6 r k1[6] x bit 5 r k1[5] x bit 4 r k1[4] x bit 3 r k1[3] x bit 2 r k1[2] x bit 1 r k1[1] x bit 0 r k1[0] x k1[7:0]: the k1[7:0] bits contain the current k1 code value when the enh bit in the mode select register is a logic 1. the contents of this register are updated when a new k1 code value (different from the current k1 code value) has been received for three consecutive frames. an interrupt may be generated when a new code value is received (using the coapse bit in the rase interrupt enable register). k1[7] is the most significant bit corresponding to bit 1, the first bit received. k1[0] is the least significant bit, corresponding to bit 8, the last bit received.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 121 address 36h: receive k2 (enh=1) bit type function default bit 7 r k2[7] x bit 6 r k2[6] x bit 5 r k2[5] x bit 4 r k2[4] x bit 3 r k2[3] x bit 2 r k2[2] x bit 1 r k2[1] x bit 0 r k2[0] x k2[7:0]: the k2[7:0] bits contain the current k2 code value when the enh bit in the mode select register is a logic 1. the contents of this register are updated when a new k2 code value (different from the current k2 code value) has been received for three consecutive frames. an interrupt may be generated when a new code value is received (using the coapse bit in the rase interrupt enable register). k2[7] is the most significant bit corresponding to bit 1, the first bit received. k2[0] is the least significant bit, corresponding to bit 8, the last bit received.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 122 register 37h: receive z1 (enh=1) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r z1[3] x bit 2 r z1[2] x bit 1 r z1[1] x bit 0 r z1[0] x z1[3:0]: the lower nibble of the first z1 byte contained in the receive stream is extracted into this register when the enh bit in the mode select register is a logic 1. the z1 byte is used to carry synchronization status messages between line terminating network elements. z1[3] is the most significant bit corresponding to bit 5, the first bit received. z1[0] is the least significant bit, corresponding to bit 8, the last bit received. an interrupt may be generated when a byte value is received that differs from the value extracted in the previous frame (using the z1e bit in the rase interrupt enable register).
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 123 register 38h: section trace control (enh=1): bit type function default bit 7 unused x bit 6 r/w rramacc 0 bit 5 r/w rtiuie 0 bit 4 r/w rtimie 0 bit 3 r/w per5 0 bit 2 r/w tnull 1 bit 1 r/w nosync 0 bit 0 r/w len16 0 len16: the section trace message length bit (len16) selects the length of the section trace message to be 16 bytes or 64 bytes. nosync: the section trace message synchronization disable bit (nosync) disables the writing of the section trace message into the trace buffer to be synchronized to the content of the message. when len16 is set high and nosync is set low, the receive section trace message byte with its most significant bit set will be written to the first location in the buffer. when len16 is set low, and nosync is also set low, the byte after the carriage return/linefeed (cr/lf) sequence will be written to the first location in the buffer. when nosync is set high, synchronization is disabled, and the section trace message buffer behaves as a circular buffer. tnull: the transmit null bit (tnull) controls the insertion of an all-zero section trace identifier message in the transmit stream. when tnull is set high, the contents of the transmit buffer are ignored and all-zeros bytes are provided to the tpop block. when tnull is set low the contents of the transmit section trace buffer is sent to tpop. tnull should be set high before changing the contents of the trace buffer to avoid sending partial messages.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 124 per5: the receive trace identifier persistence bit (per5) control the number of times a section trace identifier message must be received unchanged before being accepted. when per5 is set high, a message is accepted when it is received unchanged five times consecutively. when per5 is set low, the message is accepted after three identical repetitions. rtimie: the receive section trace identifier message mismatch interrupt enable bit (rtimie) controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state from match to mismatch and vice versa. when rtimie is set high, changes in match state activates the interrupt (intb) output. when rtimie is set low, section trace identifier message state changes will not affect intb. rtiuie: the receive section trace identifier message unstable interrupt enable bit (rtiuie) controls the activation of the interrupt output when the receive identifier message state changes from stable to unstable and vice versa. the unstable state is entered when the current identifier message differs from the previous message for six consecutive messages. the stable state is entered when the same identifier message is received for three or five consecutive messages as controlled by the per5 bit. when rtiuie is set high, changes in the received section trace identifier message stable/unstable state will activate the interrupt (intb) output. when rtiuie is set low, section trace identifier state changes will not affect intb. rramacc: the receive ram access control bit (rramacc) directs read and writes access to between the receive and transmit portion of the section trace buffers. when rramacc is set high, subsequent microprocessor read and write accesses are directed to the receive side trace buffers. when rramacc is set low, microprocessor accesses are directed to the transmit side trace buffer.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 125 register 39h: section trace status (enh=1): bit type function default bit 7 r busy 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r rtiui x bit 2 r rtiuv x bit 1 r rtimi x bit 0 r rtimv x this register reports the section trace status. rtimv: the receive section trace identifier message mismatch status bit (rtimv) reports the match/mismatch status of the identifier message framer. rtimv is set high when the accepted identifier message differs from the expected message written by the microprocessor. rtimv is set low when the accepted message matches the expected message. rtimi: the receive section trace identifier mismatch interrupt status bit (rtimi) is set high when match/mismatch status of the trace identifier framer changes state. this bit (and the interrupt) are cleared when this register is read. rtiuv: the receive section trace identifier message unstable status bit (rtiuv) reports the stable/unstable status of the identifier message framer. rtiuv is set high when the current received section trace identifier message has not matched the previous message for eight consecutive messages. rtiuv is set low when the current message becomes the accepted message. rtiui: the receive section trace identifier message unstable interrupt status bit (rtiui) is set high when stable/unstable status of the trace identifier framer
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 126 changes state. this bit (and the interrupt) are cleared when this register is read. busy: the busy bit reports whether a previously initiated indirect read or write to a message buffer has been completed. busy is set high upon writing to the section trace indirect address register, and stays high until the initiated access has completed. at which point, busy is set low. this register should be polled to determine when new data is available in the section trace indirect data register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 127 register 3ah: section trace indirect address register (enh=1) bit type function default bit 7 r/w rwb 0 bit 6 r/w a[6] 0 bit 5 r/w a[5] 0 bit 4 r/w a[4] 0 bit 3 r/w a[3] 0 bit 2 r/w a[2] 0 bit 1 r/w a[1] 0 bit 0 r/w a[0] 0 this register supplies the address used to index into section trace identifier buffers. a[6:0]: the indirect read address bits (a[6:0]) indexes into the section trace identifier buffers. when rramacc is set high, addresses 0 to 63 reference the receive capture page while addresses 64 to 127 reference the receive expected page. the receive capture page contains the identifier bytes extracted from the receive stream. the receive expected page contains the expected trace identifier message down-loaded from the microprocessor. when rramacc is set low, addresses 0 to 63 reference the transmit message buffer which contains the identifier message to be inserted into the j0 byte of the transmit stream. addresses 64 to 127 are unused and must not be accessed. rwb: the access control bit (rwb) selects between an indirect read or write access to the static page of the section trace message buffer. writing to this register initiates an external microprocessor access to the static page of the section trace message buffer. when rwb is set high, a read access is initiated. the data read can be found in the section trace indirect data register. when rwb is set low, a write access is initiated. the data in the section trace indirect data register will be written to the addressed location in the static page.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 128 register 3bh: section trace indirect data register (enh=1) bit type function default bit 7 r/w d[7] 0 bit 6 r/w d[6] 0 bit 5 r/w d[5] 0 bit 4 r/w d[4] 0 bit 3 r/w d[3] 0 bit 2 r/w d[2] 0 bit 1 r/w d[1] 0 bit 0 r/w d[0] 0 this register contains the data read from the section trace message buffer after a read operation or the data to be written into the buffer before a write operation. d[7:0]: the indirect data bits (d[7:0]) reports the data read from a message buffer after an indirect read operation has completed. the data to be written to a buffer must be set up in this register before initiating an indirect write operation.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 129 11 test features description simultaneously asserting the csb, rdb and wrb inputs low causes all output pins and the data bus to be held in a high-impedance state, provided that the mbeb input is held high. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the stxc. test mode registers (as opposed to normal mode registers) are selected when a[6] is high. test mode registers may also be used for board or module level testing. when all of the constituent tsbs within the stxc are placed in test mode 0, device inputs may be observed, and device outputs may be controlled via the microprocessor interface (refer to the "test mode 0" section below for details). table 2 - test mode register memory map a[6:0] register 00h-3fh reserved for normal registers 40h-42h reserved 43h master test 44h-47h tlop test registers 48h-4ch rlop test registers 4dh-4fh reserved 50h-53h rsop test registers 54h-57h reserved 58h-5bh tsop test registers 5ch-5eh reserved 5fh reserved 60h-63h rase test registers 63h-77h reserved 78h-7ch sptb test registers 7dh-7fh reserved
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 130 notes on register bits: 1. writing values into unused register bits has no effect. reading back unused bits can produce either a logic one or a logic zero; hence unused bits should be masked off by software when read. 2. writeable register bits are not initialized upon reset unless otherwise noted.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 131 address 43h: master test bit type function default bit 7 unused x bit 6 unused x bit 5 w force_enh 0 bit 4 w pmctst x bit 3 w mototst 0 bit 2 r/w iotst 0 bit 1 w hizdata 0 bit 0 r/w hizio 0 this register is used to enable stxc test features. all bits, except pmctst, are reset to zero by a reset of the stxc. hizio,hizdata: the hizio and hizdata bits control the tri-state modes of the stxc . while the hizio bit is a logic one, all output pins of the stxc except the data bus are held in a high-impedance state. the microprocessor interface is still active. while the hizdata bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. iotst: the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each tsb block in the stxc for board level testing. when iotst is a logic one, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the "test mode 0 details" in the "test features" section). mototst: the mototst bit is used to test the motorola interface. when mototst is logic one and the mbeb input is logic zero the scpi[2] and scpi[3] inputs are used to replace the function of e and rwb, respectively. this is done because the fixed waveform shapes assigned to the rdb_e and wrb_rwb inputs can not be used to test motorola type microprocessor
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 132 interface logic. this mode is also used to test the d.c. drive capability of the d[7:0] device pins. pmctst: the pmctst bit is used to configure the stxc for pmc's manufacturing tests. when pmctst is set to logic one, the stxc microprocessor port becomes the test access port used to run the pmc "canned" manufacturing test vectors. the pmctst bit is logically "ored" with the iotst bit, and is cleared by setting csb to logic one or by writing a logic zero. force_enh: the force_enh bit is used to test the stxc enhanced mode. when force_enh is set to logic one, the enh bit in the mode select register is forced to logic one. when force_enh is set to logic zero, the enh bit is not forced to logic one. test mode 0 in test mode 0, the stxc allows the logic levels on the device inputs to be observed through the microprocessor interface, and allows the device outputs to be controlled to either logic level through the microprocessor interface. test mode 0 is enabled by resetting the device (using the rstb input, or the master reset and identity register), and then setting the iotst bit in the master test register. the following addresses must then be written with the value 00h: 00h, 45h, 49h, 51h, 59h and 3dh. write 05h to address 01h. with the exception of the scpi[3:0] pins, applying a rising edge (logic zero to logic one transition) on the riclk and ticlk inputs followed by a read from the following locations returns the value for the indicated pins. the current states of the scpi[3:0] pins are reflected in the corresponding register locations. table 3 - test mode 0 input observation addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ah tser rser ttoh ttohen 1fh scpi[3] scpi[2] scpi[1] scpi[0] 40h rsiclk rsin 44h tdis tlow tld trdi/ taps trcpfp tifp 46h tin[7] tin[6] tin[5] tin[4] tin[3] tin[2] tin[1] tin[0] 50h rlais/ trcpclk rifp* riclk
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 133 addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 52h* rin[7] rin[6] rin[5] rin[4] rin[3] rin[2] rin[1] rin[0] 58h tsuc** tsow** tsd tlais/ trcpdat notes: * two riclk cycles are required before the read. rser must be tied low in order to observe the rin[7:0] inputs. ** to propagate tsuc and tsow, 00h then 10h must be written to 44h followed by a rising edge on ticlk. a write to one of the following locations forces each output to the value in the corresponding bit position. they need be followed by a rising edge (logic one to logic zero transition) on the riclk and ticlk inputs, with the exception of these outputs: rsow, rsd, rsdclk, rsuc, gticlk, tsdclk, tofp, tsout, scpo[5:0]. table 4 - test mode 0 output control addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 14h scpo[5] scpo[4] scpo[3] scpo[2] scpo[1] scpo[0] 1ah rtohfp rtohclk rtoh ttohfp ttohclk 40h griclk 44h tapsclk towclk tldclk 48h raps b2e* b2e* rdi/ rrcpclk lais/ rrcpdat rofp 4ah intb** rapsclk rld rldclk rlow rowclk 4bh rout[7] rout[6] rout[5] rout[4] rout[3] rout[2] rout[1] rout[0] 50h b1e* b1e* lof oof los/ rrcpfp 52h intb** rsow rsd rsdclk rsuc 58h gticlk tsdclk tofp 5ah tout[7] tout[6] tout[5] tout[4] tout[3] tout[2] tout[1] tout[0]/ fpout 5ch tsout 60h intb**
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 134 notes: * both b1e bits must be a logic one before the b1e output is asserted high. likewise, both b2e bits must be a logic one before the b2e output is asserted high. ** writing a logic one to any of the intb bits forces the intb output low provided the enable bits are set in the master control/enable register.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 135 12 functional timing figure 2 - sts-3 bit serial transmit frame pattern and data alignment ticlk/gticlk txci+/- tout[7:0] a1 (f6h) a2 (28h) a1 (f6h) a1 (f6h) a2 (28h) a2 (28h) a1 a2 txd+/- a1 a1 a2 the sts-3 bit serial transmit frame pulse and data alignment timing diagram (figure 2) illustrates bit serial operation for an sts-3 application (tser=1). the sts-3 transmit clock, txci+/-, is divided by eight to produce the byte serial transmit clock, gticlk. gticlk must be externally connected to ticlk, and bytes are then "pulled" from an upstream path overhead insertion/payload mapping device. figure 3 - sts-3 byte serial transmit frame pulse and data alignment tifp tout[7:0] tofp ticlk tin[7:0] a1 byte (sts-1 #1 - sts-1 #3) unscrambled spe a2 byte (sts-1 #1 - sts-1 #3) c1 byte (sts-1 #1 - sts-1 #3) a1 byte (sts-1 #1 - sts-1 #3) a2 byte (sts-1 #1 - sts-1 #3) c1 byte (sts-1 #1 - sts-1 #3) f6h f6h f6h 28h 28h 28h 01h 03h 02h the sts-3 transmit frame pulse and data alignment timing diagram (figure 3) illustrates the transmit frame pulse input/output alignment for an sts-3 (stm-1) frame when the byte serial interface is enabled (tser=0). the input frame pulse is aligned to the byte immediately following the last z0 byte, and it is not always necessary for this pulse to be present.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 136 figure 4 - sts-1 bit serial transmit frame pulse and data alignment a1 a2 c1 ticlk/gticlk tsiclk or txci+/- tsout scrambled sts-1 frame data tout[7:0] tofp a1 (f6h) a2 (28h) c1 (01h) txd+/- the sts-1 bit serial transmit frame pulse and data alignment timing diagram (figure 4) illustrates bit serial operation for an sts-1 application (tser=1). the sts-1 transmit clock, tsiclk or txci+/-, is divided by eight to produce the byte serial transmit clock, gticlk. gticlk must be connected externally to tclk, and bytes are "pulled" from an upstream path overhead insertion/payload mapping device. figure 5 - sts-1 byte serial transmit frame pulse and data alignment tifp tout[7:0] tofp ticlk tin[7:0] a1 a2 c1 a1 a2 c1 the sts-1 byte serial transmit frame pulse and data alignment timing diagram (figure 5) illustrates the transmit frame pulse input/output alignment for an sts-1 frame when the byte serial interface is enabled (tser=0). the input frame pulse is aligned to the byte immediately following the last z0 byte, and it is not always necessary for this pulse to be present.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 137 figure 6 - sts-3 bit serial receive frame pattern and data alignment rxd+/- rxc+/- griclk/riclk a1 c1 rout[7:0] a1 (f6h) a2 a1 a1 a2 a2 c1 c1 a1 (f6h) a1 (f6h) a2 (28h) the sts-3 bit serial receive frame pulse and data alignment timing diagram (figure 6) illustrates the receive frame alignment for an sts-3 frame when the bit serial interface is enabled (rser=1). the stxc converts the bit serial sts-3 stream, rxd+/-, to byte serial format. output griclk is a divide by eight of the bit serial line clock, rsiclk, and must be externally connected to riclk for proper operation. the rofp output is set high during the first spe byte of the first row of the sonet frame (immediately following the last z0 byte), and may be used by downstream circuitry for frame alignment. while the stxc is out-of- frame, rofp is updated based on the last frame alignment. figure 7 - sts-3 byte serial receive frame pulse and data alignment rofp rout[7:0] a1 byte (sts-1 #1 - sts-1 #3) a2 byte (sts-1 #1 - sts-1 #3) c1 byte (sts-1 #1 - sts-1 #3) spe a1 byte (sts-1 #1 - sts-1 #3) spe a2 byte (sts-1 #1 - sts-1 #3) c1 byte (sts-1 #1 - sts-1 #3) riclk rifp (fpos = 0) rin[7:0] rifp (fpos = 1) the sts-3 byte serial receive frame pulse and data alignment timing diagram (figure 7) illustrates the receive frame pulse input/output alignment for an sts-3/stm-1 frame when the byte serial interface is enabled (rser=0). the fpos bit in the master configuration register controls the expected location of the externally applied frame indication input, rifp as indicated in the diagram. the rofp output is set high during the first spe byte of the first row of the sonet frame (immediately following the last z0 byte), and may be used by downstream circuitry for frame alignment. while the stxc is out-of-frame, rofp is updated based on the last frame alignment.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 138 figure 8 - sts-1 bit serial receive frame pulse and data alignment rsin or rxd+/i rsiclk or rxc+/- griclk/riclk a1 a2 c1 rout[7:0] rofp scrambled sts-1 frame data a1 (f6h) a2 (28h) c1 (01h) the sts-1 bit serial receive frame pulse and data alignment timing diagram (figure 8) illustrates the receive frame alignment for an sts-1 frame when the bit serial interface is enabled (rser=1). the stxc converts the bit serial sts-1 stream, rsin or rxd+/-, to byte serial format. output griclk is a divide by eight of the bit serial line clock, rsiclk or rxc+/-, and must be externally connected to riclk for proper operation. the rofp output is set high during the first spe byte of the first row of the sonet frame (immediately following the last z0 byte), and may be used by downstream circuitry for frame alignment. while the stxc is out-of-frame, rofp is updated based on the last frame alignment. figure 9 - sts-1 byte serial receive frame pulse and data alignment rofp rout[7:0] spe riclk rin[7:0] rifp a1 a2 c1 a1 a2 c1 the sts-1 byte serial receive frame pulse and data alignment timing diagram (figure 9) illustrates the receive frame alignment for an sts-1 frame when the byte serial interface is enabled (rser=0). the rofp output is set high during the first spe byte of the first row of the sonet frame (immediately following the last z0 byte), and may be used by downstream circuitry for frame alignment. while the stxc is out-of-frame, rofp is updated based on the last frame alignment.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 139 figure 10 - transport overhead overwrite enable and disable k1 byte (sts-1 #1 - sts-1 #3) spe k2 byte (sts-1 #1 - sts-1 #3) k1 byte (sts-1 #1 - sts-1 #3) k2 byte (sts-1 #1 - sts-1 #3) tout[7:0] ticlk tin[7:0] tdis tdis is sampled high so k2 sts-1#3 byte value is not overwritten tdis is sampled low so k1 sts-1#1 byte value is overwritten the transport overhead overwrite enable and disable timing diagram (figure 10) illustrates the operation of the toh overwrite disable feature. it is assumed that the ttohen input is low. the diagram shows input tdis sampled low during the k1 sts-1 #1 byte and then sampled high during the k2 sts-1 #3 byte. since tdis was low the byte value in the k1 sts-1 #1 byte position for the output data tout[7:0] is overwritten with the value shifted in on taps (or the value contained in the transmit k1/k2 registers depending on the level of the apsreg bit in the master control/enable register). however, the byte value in the k2 sts-1 #3 position for the output data tout[7:0] is not overwritten with an all zero byte because tdis was sampled high during this byte position on the input data stream. an error insertion feature is also provided for the b1 and b2 byte positions. when tdis is held high during any or all of the b1 or b2 byte positions, the associated data sampled on tin[7:0] is used as an error insertion mask. a logic one in a given bit position causes the inversion of the corresponding b1 or b2 bit position prior to transmission. a logic zero in a given bit position causes the corresponding b1 or b2 bit position to be transmitted uncorrupted. figure 11 - in frame declaration (bit serial interface, rser=1) rxd+/- ???? oof a1 a1 a2 a2 a2 c1 c1 c1 a1 a1 a1 a2 a2 a2 c1 c1 c1 a1 ???? ???? 125 s between framing pattern occurrences griclk/riclk ????
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 140 the in frame declaration (bit serial interface, rser = 1) timing figure 11) illustrates the declaration of in-frame by the stxc when processing a 155.52 mbit/s stream on rxd+/rxd-. the stxc searches the incoming stream for an occurrence of the 48 bit framing pattern (three a1 bytes followed by three a2 bytes). in frame is declared when the framing pattern (or a 12 bit subset if the algo2 register bit is set) is observed for the second time, 125 s after the first occurrence, and in the intervening period (125 s), no occurrences of the 48 bit framing pattern were detected. this algorithm results in a maximum average reframe time of 250 s in the absence of mimic framing patterns. griclk is generated by dividing the bit serial clock (rxc+, rxc-) by eight and must be connected externally to the riclk input. the falling edge of riclk is used to update oof. figure 12 - in frame declaration (byte serial interface, rser=0) rin[7:0] ???? oof a1 a1 a2 a2 a2 c1 c1 c1 a1 a1 a1 a2 a2 a2 c1 c1 c1 a1 ???? ???? 125 s between framing pattern occurrences rifp riclk ???? ???? the in frame declaration (byte serial interface, rser=0) timing diagram (figure 12) illustrates the declaration of in-frame by the stxc when processing a 19.44 mbyte/s stream on rin[7:0]. an upstream serial to parallel converter, or byte interleaved demultiplexer indicates the frame location using the rifp input. the byte position marked by rifp may be controlled using the fpos bit in the master configuration register. figure 12 illustrates the rifp alignment when fpos is set to a logic zero. the frame verification is initialized by a pulse on rifp while the stxc is out of frame. in frame is declared if the framing pattern is observed in the correct byte positions in the following frame, and in the intervening period (125 s) no additional pulses were present on rifp. the stxc ignores pulses on rifp while in frame. this algorithm results in a maximum average reframe time of 250 s in the absence of mimic framing patterns.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 141 figure 13 - out of frame declaration rin[7:0] oof a1 a1 a2 a2 a2 a1 riclk ???? ???? ???? four consecutive frames containing framing pattern errors ???? a1 a1 a2 a2 a2 a1 ???? a1 a1 a2 a2 a2 a1 ???? a1 a1 a2 a2 a2 a1 c1 c1 c1 a1/a2 error ???? ???? ???? ???? a1/a2 error a1/a2 error a1/a2 error the out of frame declaration timing diagram (figure 13) illustrates the declaration of out of frame. in an sts-3 (stm-1) stream, the framing pattern is a 48 bit sequence that repeats once per frame (for the purposes of oof declaration, the framing pattern may be modified using the algo2 bit in the rsop control register). out of frame is declared when one or more errors are detected in this pattern for four consecutive frames as illustrated. in the presence of random data, out of frame will normally be declared within 500 s. figure 14 - loss of signal declaration/removal rin[7:0] los riclk ???? ???? ???? 20 2.5 s ???? ???? a1 a1 a2 a2 a2 a1 ???? a2 a2 a2 c1 c1 c1 ???? ???? ???? ???? ???? two valid framing patterns (125 s) the loss of signal declaration/removal timing diagram (figure 14) illustrates the operation of the los output. los is declared when a violating period of all zeros (20 2.5 s) is observed on rin[7:0] (note the same criteria applies to rxd+/- and rsin when processing bit serial streams). los is removed when two valid framing patterns are observed, and in the intervening period (125 s), no violating periods of all zeros is observed.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 142 figure 15 - loss of frame declaration/removal oof riclk ???? ???? 3 ms ???? ???? ???? ???? ???? lof ???? ???? ???? ???? 3 ms the loss of frame declaration/removal timing diagram (figure 15) illustrates the operation of the lof output. lof is an integrated version of oof. lof is declared when an out of frame condition persists for 3 ms. lof is removed when an in frame condition persists for 3 ms. figure 16 - line ais and line rdi declaration/removal rin[7:0] lais rdi k2 k1 riclk ???? ???? ???? 625 s (5 frames) ???? c1 c1 ???? k2 k1 ???? c1 c1 ???? ???? ???? ???? ???? ???? 625 s (5 frames) c1 c1 the line ais and line rdi declaration/removal timing diagram (figure 16) illustrates the operation of the lais and rdi outputs. a byte serial sts-3 (stm- 1) stream is shown for illustrative purposes. lais (rdi) is declared when the binary pattern '111' ('110') is observed in bits 6,7, and 8 of the k2 byte for three or five consecutive frames. lais (rdi) is removed when any pattern other than the binary pattern '111' ('110') is observed in bits 6,7, and 8 of the k2 byte for three or five consecutive frames.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 143 figure 17 - transmit overhead clock and data alignment towclk ticlk tofp k1 b1 taps b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 k2 tapsclk e1, f1, e2 b1 b2 b3 b5 b6 b7 b8 tsow tsuc tlow b4 tofp towclk tapsclk approx 750 ns the transmit overhead clock and data alignment timing diagram (figure 17) shows the relationship between the tsow, tlow, tsuc and taps serial data inputs and their associated clocks, towclk and tapsclk. towclk is a 72 khz 50% duty cycle clock that is gapped to produce a 64 khz nominal rate and is aligned as shown in the timing diagram. tapsclk is a 144 khz 50% duty cycle clock that is gapped to produce a 128 khz nominal rate and is aligned as shown in the timing diagram. the e1, e2, f1, k1 and k2 bytes shifted into the stxc on tsow, tlow, tsuc, and taps in the frame shown are inserted in the corresponding transport overhead channels in the next frame.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 144 figure 18 - receive overhead clock and data alignment rowclk riclk rofp k1 b1 raps b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 k2 rapsclk e1, f1, e2 b1 b2 b3 b5 b6 b7 b8 rsow rlow rsuc b4 rofp rowclk rapsclk approx 750 ns the receive overhead alignment timing diagram (figure 18) shows the relationship between the rsow, rsuc, rlow, and raps serial data outputs and their associated clocks, rowclk and rapsclk. rowclk is a 72 khz 50% duty cycle clock that is gapped to produce a 64 khz nominal rate and is aligned as shown in the timing diagram. rapsclk is a 144 khz 50% duty cycle clock that is gapped to produce a 128 khz nominal rate and is aligned as shown in the timing diagram. the e1, f1, e2, k1 and k2 bytes shifted out of the stxc on rsow, rsuc, rlow, and raps in the frame shown are extracted from the corresponding transport overhead channels in the previous frame.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 145 figure 19 - transmit data link clock and data alignment row 1 bytes row 6 bytes row 5 bytes row 4 bytes row 3 bytes row 7 bytes row 2 bytes row 9 bytes row 8 bytes tofp tldclk approx. 2 mhz dlclk bursts tldclk tld b2 b1 b3 b4 b5 b6 b7 b8 b2 b1 b3 b4 b5 b6 b7 b8 b2 b1 b3 b4 b5 b6 b7 b8 tld tsdclk b1 tsd b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 the transmit data link clock and data alignment timing diagram (figure 19) shows the relationship between the tsd, and tld serial data inputs, and their associated clocks, tsdclk and tldclk respectively. tsdclk is a 216 khz, 50% duty cycle clock that is gapped to produce a 192 khz nominal rate that is aligned with tofp as shown in the timing diagram. tldclk is a 2.16 mhz, 67%(high)/33%(low) duty cycle clock that is gapped to produce a 576 khz nominal rate that is aligned with tofp as shown in the timing diagram. tsd (tld) is sampled on the rising tsdclk (tldclk) edge. the d1-d3, and d4- d12 bytes shifted into the stxc in the frame shown are inserted in the corresponding transport overhead channels in the following frame.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 146 figure 20 - receive data link clock and data alignment row 1 bytes row 6 bytes row 5 bytes row 4 bytes row 3 bytes row 7 bytes row 2 bytes row 9 bytes row 8 bytes rofp rldclk approx. 2 mhz dlclk bursts rldclk rld b2 b1 b3 b4 b5 b6 b7 b8 b2 b1 b3 b4 b5 b6 b7 b8 b2 b1 b3 b4 b5 b6 b7 b8 rld rsdclk b1 rsd b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 the receive data link clock and data alignment timing diagram (figure 20) shows the relationship between the rsd, and rld serial data outputs, and their associated clocks, rsdclk and rldclk. rsdclk is a 216 khz, 50% duty cycle clock that is gapped to produce a 192 khz nominal rate that is aligned with rofp as shown in the timing diagram. rldclk is a 2.16 mhz, 67%(high)/33%(low) duty cycle clock that is gapped to produce a 576 khz nominal rate that is aligned with rofp as shown in the timing diagram. rsd (rld) is updated on the falling rsdclk (rldclk) edge. the d1-d3, and d4- d12 bytes shifted out of the stxc in the frame shown are extracted from the corresponding receive line overhead channels in the previous frame.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 147 figure 21 - b1 and b2 error event occurrence rofp row 1 bytes row 6 bytes row 5 bytes row 4 bytes row 3 bytes row 7 bytes row 2 bytes row 9 bytes row 8 bytes b2e 1st of 8 possible b1e events per frame during row 8 2nd of 24 possible b2e events per frame 24th of 24 possible b2e events per frame b2e b1e b1e 8th of 8 possible b1e events per frame 1st of 24 possible b2e events per frame during row 6 the b1 and b2 error event occurrence timing diagram (figure 21) shows the location of b1 and b2 error events in an sts-3 frame. up to 8 b1 errors and 24 b2 errors may be detected per frame. the b1 and b2 error clocks, b1e and b2e, pulse once for every b1 and b2 error detected. these signals may be used to accumulate b1 and b2 errors externally.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 148 figure 22 - transport overhead extraction rtohfp a1 byte a2 byte a2 byte a1 byte a1 byte e2 byte (unused) e2 byte (unused) rtohclk rtohclk a1 byte a1 byte ???? ???? rtoh b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 ???? rtohfp the transport overhead extraction timing diagram (figure 22) illustrates the transport overhead extraction interface for sts-3. the transport overhead extraction clock, rtohclk is nominally a 5.184 mhz clock (1.728 mhz for an sts-1 stream), and is derived from the receive line clock, riclk. the entire transport overhead (the complete 9 row by 9 column structure) is extracted for the sts-3 stream and is serialized on rtoh over a frame period (125 s).
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 149 figure 23 - transport overhead insertion ttohfp a1 byte a2 byte a2 byte a1 byte a1 byte e2 byte (unused) e2 byte (unused) ttohclk ttoh b8 ttohclk a1 byte a1 byte ???? ???? b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 b1 ttohen ???? ttohfp the transport overhead insertion timing diagram (figure 23) illustrates the transport overhead insertion interface. output ttohclk is nominally a 5.184 mhz clock (1.728 mhz for an sts-1 stream), and is used to update output ttohfp, and to sample input ttoh and ttohen. it is assumed that the tdis input is held low. a high level on tdis takes precedence over the transport overhead insertion interface. the value sampled on ttohen during the first overhead bit position of a given set of overhead bytes determines whether the value sampled on ttoh is inserted in the sts-3 stream. in figure 22, ttohins is held high during the bit 1 position of the a1 byte in the ttoh stream. the eight bit values sampled on input ttoh during the first a1 byte period are inserted in the first a1 byte position in the sts-3 (stm-1) stream. similarly, ttohins is held low during the bit 1 position of the second a1 byte. the default value (f6h) is inserted in the second a1 byte position in the sts-3 (stm-1) stream. an error insertion feature is also provided for the b1, and b2 byte positions. when ttoh is held high during any of the bit positions corresponding to these bytes, the corresponding bit is inverted before being inserted in the sts-3 (stm- 1) stream (ttohen must be sampled high during the first bit position to enable the error insertion mask).
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 150 figure 24 - transmit ring control port trcpfp sendrdi trcpclk reserved for line febe indications trcpdat trcpfp sendais : reserved for future use : reserved for line febe indication trcpdat the transmit ring control port timing diagram (figure 24) illustrates the operation of the transmit ring control port when the ring control ports are enabled (using the rcp bit in the stxc control/enable register). the control port timing is provided by the trcpclk input. trcpfp and trcpdat are sampled on the rising edge of trcpclk. trcpfp is used to distinguish the bit positions carrying maintenance signal control information (trcpfp is high) from the bit positions carrying line rei indications (trcpfp is low). trcpfp is high for 21 bit positions once per frame 125 s). currently, only the last two bit positions are used. these bit positions control the insertion of line rdi and line ais maintenance signals as illustrated in figure 24. the remaining 19 bit positions are reserved for future stxc feature enhancements.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 151 figure 25 - receive ring control port rrcpfp sendrdi rrcpclk reserved for line febe indications rrcpdat rrcpfp sendais psbfv psbfi coapsi b8 b7 b6 b5 b4 b3 b2 b1 b8 b7 b6 b5 b4 b3 b2 b1 filtered k1 byte filtered k2 byte rrcpdat the receive ring control port timing diagram (figure 25) illustrates the operation of the receive ring control port when the ring control ports are enabled (using the rcp bit in the stxc control/enable register). the control port timing is provided by the rrcpclk input. rrcpfp and rrcpdat are updated on the falling edge of rrcpclk. rrcpfp is used to distinguish the bit positions carrying alarm status and maintenance signal control information (rrcpfp is high) from the bit positions carrying line rei indications (rrcpfp is low). rrcpfp is high for 21 bit positions once per 125 s frame. the first 16 bit positions contain the aps channel byte values after filtering (the k1 and k2 values have been identical for at least three consecutive frames). the 17th bit position, coapsi, is high for one frame when a new aps channel byte value (after filtering) is received. the 18th and 19th bit positions contain the current protection switch byte failure alarm status. psbfi is high for one frame when a change in the protection switch byte failure alarm state is detected. psbfv contains the real-time active high state value of the protection switch byte failure alarm. the 20th and 21st bit positions control the insertion of the line ais and line rdi maintenance signals in a mate stxc. the sendrdi bit position is controlled by the logical or of the loss of signal, loss of frame and line ais alarms, or by the srdi bit in the ring control register. the sendais bit position is controlled by the sais bit in the ring control register. while rrcpfp is low, rrcpdat is high for one rrcpclk cycle for each received rei indication.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 152 13 operation 13.1 bit error rate monitor the receive aps, synchronization extractor and bit error (rase) block counts and monitors line bip errors over programmable periods of time (window size). the rase contains two bit error rate monitors (berm), one monitors the signal fail threshold crossing alarm, and the other monitors the signal degrade threshold crossing alarm. the tables below give calculated values that are appropriate for both the sf berm and sd berm. typically, the sf threshold will be configured for a ber of 10 -3 or 10 -4 and the sd threshold will be configured between 10 -5 and 10 -9 . for all of the tables below, the saturation threshold should be disabled by setting smode=0. all of the recommended values below meet the various requirements for detection/clearing and (where applicable) false detection/clearing. in the case of the sdh recommendations, the detection (clearing) thresholds were chosen between the minimum and maximum values established by the detection and false detection requirements. in the case of the sonet recommendations, the detection thresholds were chosen at their maximum value, and the clearing thresholds at their minimum. the cmode column corresponds to the values that should be written to the sfcmode and sdcmode bits in the rase configuration/control register. the accumulation period column represents the values that should be written to the rase sf accumulation registers and the rase sd accumulation period registers. . the detection threshold column represents the values that should be written to the rase sf detection threshold registers and the rase sd detection threshold registers. the clearing threshold column represents the values that should be written to the rase sf clearing threshold registers and the rase sd clearing threshold period registers.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 153 table 5 - rase-berm configuration for sdh stm-0 ber evaluation period (s) cmode (sfcmode/ sdcmode) accumulation period (sfsap/sdsap) detection threshold (sfdth/sddth) clearing threshold (sfcth/sdcth ) 1.0e-03 0.01 0 00000a 0d7 04a 1.0e-04 0.1 0 000064 0d7 04a 1.0e-05 1 0 0003e8 0d7 04a 1.0e-06 10 0 002710 0d7 04a 1.0e-07 100 0 0186a0 0d7 04a 1.0e-08 1000 0 0f4240 0d7 04a 1.0e-09 10000 0 989680 0d7 04a table 6 - rase-berm configuration for sdh stm-1 ber evaluation period (s) cmode (sfcmode/ sdcmode) accumulation period (sfsap/sdsap) detection threshold (sfdth/sddth) clearing threshold (sfcth/sdcth ) 1.0e-03 0.01 0 00000a 2a2 0ca 1.0e-04 0.1 0 000064 2a2 0ca 1.0e-05 1 0 0003e8 2a2 0ca 1.0e-06 10 0 002710 2a2 0ca 1.0e-07 100 0 0186a0 2a2 0ca 1.0e-08 1000 0 0f4240 2a2 0ca 1.0e-09 10000 0 989680 2a2 0ca
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 154 table 7 - rase-berm configuration for sonet sts-1 ber evaluation period (s) cmode (sfcmode/ sdcmode) accumulation period (sfsap/sdsap) detection threshold (sfdth/sddth) clearing threshold (sfcth/sdcth ) 1.0e-03 0.01* 1 00000a 0d9 1b5 1.0e-04 0.04 1 000028 0a7 0b8 1.0e-05 0.3 1 00012c 084 08e 1.0e-06 3 1 000bb8 084 08e 1.0e-07 30 1 007530 084 08e 1.0e-08 250 1 03d090 06d 078 1.0e-09 2000 1 1e8480 055 061 *detection time objectives and false detection objectives cannot be met simultaneously for sts-1 with a 10 -3 bit error rate. the given values meet the detection time requirements with a 0.999 probability, and also meet the false detection objectives. table 8 - rase-berm configuration for sonet sts-3 ber evaluation period (s) cmode (sfcmode/ sdcmode) accumulation period (sfsap/sdsap) detection threshold (sfdth/sddth) clearing threshold (sfcth/sdcth) 1.0e-03 0.008 1 000008 245 3be 1.0e-04 0.013 1 00000d 0a3 0b4 1.0e-05 0.1 1 000064 084 08e 1.0e-06 1 1 0003e8 084 08e 1.0e-07 10 1 002710 084 08e 1.0e-08 83 1 014438 06d 077 1.0e-09 667 1 0a2d78 055 061
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 155 14 absolute maximum ratings table 9 - stxc absolute maximum ratings ambient temperature under bias -40c to +85c storage temperature -40c to +125c supply voltage -0.5v to +6.0v voltage on any pin -0.5v to v dd +0.5v static discharge voltage 500 v latch-up current 100 ma dc input current 20 ma lead temperature +230c absolute maximum junction temperature +150c
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 156 15 d.c. characteristics (t a = -40c to +85c) table 10 - stxc d.c. characteristics symbol parameter min typ max units conditions v dd power supply 4.75 5 5.25 volts applies to vddi[2:0], vddo[7:0], tav d 1 , tav d 2 and tavd3. a vd power supply 4.75 5 5.25 volts v tav d 4 tx analog reference supply voltage 4.75 5.25 volts | v pih -v pil | =600 mv, pecl inputs ac coupled. v ravd rx analog reference supply voltage 4.75 5.25 volts | v pih -v pil | =600 mv, pecl inputs ac coupled. v il input low voltage (ttl only) -0.5 0.8 volts guaranteed input low voltage v ih input high voltage (ttl only) 2.0 v dd +0.5 volts guaranteed input high voltage v pswg input voltage swing (pecl only) 550 1000 mv txci+/-, rxd+/- and rxc+/- a.c. coupled v ol output or bidirectional low voltage (ttl only) 0.1 0.4 volts v pol output low voltage (pecl only) v te rm -0.6 volts note 6 symbol parameter min typ max units conditions
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 157 symbol parameter min typ max units conditions v oh output or bidirectional high voltage (ttl only) vdd - 0.5 volts v t+ reset input high voltage 3.5 volts v t- reset input low voltage 0.8 volts v th reset input hysteresis voltage 1.0 volts i ilpu input low current +20 +83 +200 a v il = gnd, notes 1, 3 i ihpu input high current -10 0 +10 a v ih = v dd , notes 1, 3 i ilpd input low current -10 0 +10 a v il = gnd, notes 4, 3 i ihpd input high current -200 -83 -20 a v ih = v dd , notes 4, 3 i il input low current -10 0 +10 a v il = gnd, notes 2, 3 i ih input high current -10 0 +10 a v ih = v dd , notes 2, 3 c in input capacitance 5 pf excluding package, package typically 2 pf for mqfp c out output capacitance 5 pf excluding package, package typically 2 pf for mqfp
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 158 symbol parameter min typ max units conditions c io bidirectional capacitance 5 pf excluding package, package typically 2 pf for mqfp i tav d 4 tx reference supply current 2.5 ma i ravd rx reference supply current 3.5 ma symbol parameter min typ max units conditions i vt2 tx drive level reference input current 3.5 ma i tav d 1 , 2,3 total pecl driver supply current 44 ma i ddop1 operating current sts-3 bit serial mode enabled 130 190 ma v dd = 5.25 v, outputs unloaded, rxc+/- = 155.52 mhz, txci+/- = 155.52 mhz, random data i ddop2 operating current sts-3 byte serial mode enabled 31 60 ma v dd = 5.25 v, outputs unloaded, riclk, ticlk = 19.44 mhz, random data, avd = 0 v. i ddop3 operating current sts-1 bit serial mode enabled (pecl outputs) 150 170 ma v dd = 5.25 v, outputs unloaded, rsiclk, tsiclk = 51.84 mhz, random data
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 159 symbol parameter min typ max units conditions i ddop4 operating current sts-1 byte serial mode enabled 26 40 ma v dd = 5.25 v, outputs unloaded, riclk, ticlk = 6.48 mhz, random data, avd = 0 v. notes on d.c. characteristics: 1. input pin or bidirectional pin with internal pull-up resistor. 2. input pin or bidirectional pin without internal pull-up resistor 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. input pin or bidirectional pin with internal pull-down resistor. 5. typical values are given as a design aid. the product is not tested to these values. 6. the pecl output low voltage is specified relative to the termination voltage (vterm) as illustrated below: figure 26 - pecl output low voltage txdo+/-, txd+/- zo vcc txdo+/-, txd+/- zo vterm r1 r2 r1 // r2 = zo zo (r1 + r2) r2 vterm = * vcc
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 160 this specification is applicable when the stxc is operated as illustrated in the interface examples section (a 50 w controlled impedance environment with r1 = 59 w and r2 = 312 w ).
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 161 16 microprocessor interface timing characteristics (t a = -40c to +85c, v dd = 5 v 5%) table 11 - microprocessor interface read access (figure 27, figure 28) symbol parameter min max units ts ar address to valid read set-up time 25 ns th ar address to valid read hold time 20 ns ts alr address to latch set-up time 20 ns th alr address to latch hold time 20 ns tv l valid latch pulse width 20 ns ts lr latch to read set-up 0 ns th lr latch to read hold 20 ns ts rwb rwb to read set-up 25 ns th rwb rwb to read hold 20 ns tp rd valid read to valid data propagation delay 80 ns tz rd valid read negated to output tri-state 20 ns tz inth valid read negated to output tri-state 50 ns
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 162 figure 27 - microprocessor interface read access timing (intel mode) (csb+rdb) intb tz inth valid data d[7:0] tp rd tz rd ts ar th ar valid address a[6:0] ale ts alr tv l ts lr th alr th lr
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 163 figure 28 - microprocessor interface read access timing (motorola mode) intb tz int (csb & e) valid data d[7:0] tp rd tz rd valid address a[6:0] ale ts alr tv l ts lr th alr th lr th ar rwb ts rwb th rwb ts ar
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 164 notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. a. in intel mode, a valid read cycle is defined as a logical or of the csb and the rdb signals. b. in motorola mode, a valid read cycle is defined as a logical and of the e signal, the rwb signal and the inverted csb signal. 4. microprocessor interface timing applies to normal mode register accesses only. 5. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alr , th alr , tv l , and ts lr are not applicable. 6. parameter th ar and ts ar are not applicable if address latching is used. 7. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 8. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 165 table 12 - microprocessor interface write access (figure 29, figure 30) symbol parameter min max units ts aw address to valid write set-up time 25 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 20 ns th alw address to latch hold time 20 ns tv l valid latch pulse width 20 ns ts lw latch to write set-up 0 ns th lw latch to write hold 20 ns ts rwb rwb to write set-up 25 ns th rwb rwb to write hold 20 ns th dw data to valid write hold time 20 ns th aw address to valid write hold time 20 ns tv wr valid write pulse width 40 ns
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 166 figure 29 - microprocessor interface write access timing (intel mode) th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+wrb) a[6:0] valid address ale tv l ts alw ts lw th alw th lw
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 167 figure 30 - microprocessor interface write access timing (motorola mode) tv wr (csb & e) a[6:0] valid address th dw valid data d[7:0] ts dw ale tv l ts alw ts lw th alw th lw th aw ts aw rwb ts rwb th rwb notes on microprocessor interface write timing: 1. in intel mode, a valid write cycle is defined as a logical or of the csb and the wrb signals. a. in motorola mode, a valid write cycle is defined as a logical and of the e signal, the inverted rwb signal and the inverted csb signal. 2. microprocessor timing applies to normal mode register accesses only.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 168 3. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alw , th alw , tv l , and ts lw are not applicable. 4. parameters th aw and ts aw are not applicable if address latching is used. 5. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 169 17 stxc timing characteristics (t a = -40c to +85c, v dd = 5 v 5%) 17.1 input timing table 13 - receive input (figure 31) symbol description min max units riclk frequency (nominally 6.48 mhz, 19.44 mhz) 20 mhz riclk duty cycle 33 67 % ts rin rin[7:0] set-up time to riclk 2 ns th rin rin[7:0] hold time to riclk 3 ns ts rlais rlais set-up time to riclk 2 ns th rlais rlais hold time to riclk 3 ns ts rifp rifp set-up time to riclk 2 ns th rifp rifp hold time to riclk 3 ns
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 170 figure 31 - receive input timing ts th rin rin riclk rin[7:0] ts th rifp rifp rifp ts th rlais rlais rlais table 14 - transmit input (figure 32) symbol description min max units ticlk frequency (nominally 6.48 mhz 19.44 mhz mhz) 20 mhz ticlk duty cycle 33 67 % ts tin tin[7:0] set-up time to ticlk 2 ns th tin tin[7:0] hold time to ticlk 3 ns ts tdp tdp, tplset-up time to ticlk 10 ns th tdp tdp, tpl hold time to ticlk 5 ns ts tfpin tifp set-up time to ticlk 2 ns th tfpin tifp hold time to ticlk 3 ns ts tdis tdis set-up time to ticlk 2 ns th tdis tdis hold time to ticlk 3 ns ts trdi trdi set-up time to ticlk 10 ns
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 171 symbol description min max units th trdi trdi hold time to ticlk 5 ns ts tlais tlais set-up time to ticlk 10 ns th tlais tlais hold time to ticlk 5 ns ts tld tld set-up time to tldclk 30 ns th tld tld hold time to tldclk 0 ns ts tsd tsd set-up time to tsdclk 30 ns th tsd tsd hold time to tsdclk 0 ns ts tow tsow, tlow, tsuc set-up time to towclk 30 ns th tow tsow, tlow, tsuc hold time to towclk 0ns ts taps taps set-up time to tapsclk 30 ns th taps taps hold time to tapsclk 0 ns ts ttoh ttohclk set-up time to ttoh, ttohen 30 ns th ttoh ttohclk hold time to ttoh, ttohen 0ns
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 172 figure 32 - transmit input ttoh, tohen tsd ts th tld tld tldclk tld ts th tow tow towclk tsow tsuc tlow ts th tifp tifp tifp ts th trdi trdi trdi ts th tlais tlais tlais ts th taps taps tapsclk taps ts th ttoh ttoh ttohclk ts th tdis tdis tdis ts th tsd tsd tsdclk ts th tin tin tin[7:0] tclk ts th tdp tdp tdp, tpl
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 173 table 15 - sts-3 bit serial input (figure 33) symbol description min max units rxc+/- frequency (nominally 155.52 mhz) 156 mhz rxc+/- duty cycle 40 60 % txci+/- frequency (nominally 155.52 mhz) 156 mhz txci+/- duty cycle 40 60 % ts rxd rxd+/- set-up time to rxc+/- 2 ns th rxd rxd+/- hold time to rxc+/- 1 ns figure 33 - sts-3 bit serial input ts th rxd rxd rxc+/- rxd+/-
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 174 table 16 - sts-1 input (figure 34) symbol description min max units rsiclk frequency (nominally 51.84 mhz) 52 mhz rsiclk duty cycle 33 67 % tsiclk frequency (nominally 51.84 mhz) 52 mhz tsiclk duty cycle 33 67 % ts rsin rsin set-up time to rsiclk 3 ns th rsin rsin hold time to rsiclk 2 ns figure 34 - sts-1 input ts th rsin rsin rsiclk rsin
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 175 table 17 - transmit ring control port input (figure 35) symbol description min max units trcpclk frequency (nominally 3.24 mhz) 4mhz trcpclk duty cycle 33 67 % ts trcpfp trcpfp set-up time to trcpclk 10 ns th trcpfp trcpfp hold time to trcpclk 10 ns ts trcpd trcpdat set-up time to trcpclk 10 ns th trcpd trcpdat hold time to trcpclk 10 ns figure 35 - transmit ring control port input ts th trcpfp trcpfp trcpclk trcpfp ts th trcpd trcpd trcpdat notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 176 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 3. when a set-up time is specified between a pecl input and a clock, the set- up time is the time in nanoseconds from the crossing point of the input to the crossing point of the clock. 4. when a hold time is specified between a pecl input and a clock, the hold time is the time in nanoseconds from the crossing point of the input to the crossing point of the clock. 17.2 output timing table 18 - receive output timing (figure 36) symbol description min max units tp rout riclk high to rout[7:0] valid prop delay 425ns tp rdp riclk high to rdp valid prop delay 435ns tp rofp riclk high to rofp valid prop delay 425ns tp ralm riclk high to oof, lof, los, lais, rdi valid prop delay 430ns tp rld rldclk low to rld valid prop delay -15 20 ns tp rsd rsdclk low to rsd valid prop delay -15 20 ns tp row rowclk low to rsow, rsuc, rlow valid prop delay -250 +250 ns tp raps rapsclk low to raps valid prop delay -15 20 ns tp rtoh rtohclk low to rtoh and rtohfp valid prop delay -15 20 ns
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 177 figure 36 - receive output timing riclk rout rout[7:0] tp rldclk rld rld tp rowclk row rsow rsuc rlow tp rapsclk raps raps tp rtohclk rtoh rtoh rtohfp tp rofp rofp tp alm oof, lof, los, lais, rdi tp rsdclk rsd rsd tp rdp tp rdp
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 178 table 19 - transmit output timing (figure 37) symbol description min max units tptout ticlk high to tout[7:0] valid prop delay 220ns tptofp ticlk high to tofp valid prop delay 220ns tpttohfp ttohclk low to ttohfp valid prop delay -20 20 ns figure 37 - transmit output timing ticlk tout tout[7:0] tp tofp tofp tp ttohclk ttohfp ttohfp tp
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 179 table 20 - sts-3 bit serial output (figure 38) symbol description min max units tp txd txco+/- low to txd+/- valid prop delay -1 1 ns tp txco txci+/- high to txco+/- valid prop delay 220ns figure 38 - sts-3 bit serial output timing txco+/- txd txd+/- tp table 21 - sts-1 output (figure 39) symbol description min max units tptsout tsiclk high to tsout valid prop delay * 215ns * into a 30pf load. figure 39 - sts-1 output timing tsiclk tsout tsout tp
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 180 table 22 - receive ring control port output (figure 40) symbol description min max units tp rrcpfp rrcpclk high to rrcpfp valid prop delay -15 20 ns tp rrcpd rrcpclk high to rrcpdat valid prop delay -15 20 ns figure 40 - ring control port output rrcpclk rrcpfp rrcpfp tp rrcpd rrcpdat tp notes on output timing: 1. ttl output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. pecl output propagation delay time is the time in nanoseconds from the crossing point of the reference signal to the crossing point of the output. 3. maximum and minimum ttl output propagation delays are measured with a 50 pf load on the outputs, with the exception of tprout , tptout , and tptsout , which are measured with a 30 pf load on the outputs. 4. maximum and minimum pecl output propagation delays are measured with the pecl outputs terminated into a 50 w equivalent load.
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 181 18 ordering and thermal information table 23 - stxc ordering information part no. description pm5343-ri 160 copper leadframe metric quad flat pack (mqfp) table 24 - stxc thermal information part no. ambient temperature theta ja theta jc pm5343-ri -40c to 85c 45 c/w 15 c/w
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 182 19 mechanical information figure 41 - 160 pin copper leadframe metric quad flat pack (r suffix): e d d1 1 designator pin 1 e1 e 160 0.65 0.10 0.38 0.22 1.03 0.88 body size: ccc b e l e1 e d1 d a2 a1 a dim. max. min. nom. package type: 160 pin metric plastic quad flatpack-mqfp 3.42 4.07 0.25 0.39 3.17 3.42 30.95 31.20 31.45 27.85 28.00 28.10 30.95 31.20 31.45 27.85 28.00 28.10 0.73 8-12 deg a 8-12 deg a2 see detail a 3.68 28 x 28 x 3.49 mm gage plane, 0.25 above seating plane. detail a 0-7 deg plane seating 0.13-0.23 c l .25 a 0-10 deg. ccc c lead coplanarity notes: 1) all dimensions in millimeter. b standoff a1 3) foot length "l" is measured at c with tolerances as indicated. 2) dimensions shown are nominal
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver proprietary and confidential to pmc-sierra inc., and for its customers internal use 183 notes
pm5343 stxc data sheet pmc-930303 issue 6 sonet/sdh transport overhead transceiver none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 1998 pmc-sierra, inc. pmc-930303 (p6) ref pmc-911006(p8) issue date: september 1998 proprietary and confidential to pmc-sierra inc., and for its customers internal use contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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